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Re: [PATCH] x86/PVH: expose OEMx ACPI tables to Dom0


  • To: Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Wed, 26 Mar 2025 10:45:18 +0100
  • Autocrypt: addr=jbeulich@xxxxxxxx; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL
  • Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • Delivery-date: Wed, 26 Mar 2025 09:45:28 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 26.03.2025 10:21, Roger Pau Monné wrote:
> On Wed, Mar 26, 2025 at 09:45:09AM +0100, Jan Beulich wrote:
>> What they contain we don't know, but we can't sensibly hide them. On my
>> Skylake system OEM1 (with a description of "INTEL  CPU EIST") is what
>> contains all the _PCT, _PPC, and _PSS methods, i.e. about everything
>> needed for cpufreq. (_PSD interestingly are in an SSDT there.)
>>
>> Further OEM2 there has a description of "INTEL  CPU  HWP", while OEM4
>> has "INTEL  CPU  CST". Pretty clearly all three need exposing for
>> cpufreq and cpuidle to work.
>>
>> Fixes: 8b1a5268daf0 ("pvh/dom0: whitelist PVH Dom0 ACPI tables")
>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
> 
> Reviewed-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>

Thanks.

>> ---
>> Sadly the commit above says nothing at all about the criteria used by
>> which tables would want to be whitelisted.
> 
> I think at that point it was mostly an allow list that enabled me to
> boot PVH on the systems I was testing.  I don't think it was intended
> to be complete, but rather something that we would expand as needed.
> There where many and bigger missing pieces of PVH dom0 when that was
> committed.

To be frank, with that it was premature to declare PVH Dom0 fully supported.
This aspect also isn't mentioned in the caveats in SUPPORT.md.

>> Further tables on said system
>> which weren't blacklisted prior to that commit, yet which also aren't
>> whitelisted are DBGP, DBG2, FIDT, LPIT, MIGT, MSCT, NITR, PCCT, RASF,
>> SVOS, UEFI, WDDT, and WSMT. Even without diving into the details of any
>> of them it seems pretty clear to me that at least some would want
>> whitelisting, too.
> 
> I cannot find any reference about: FIDT, MIGT, NITR, SVOS and WDDT in
> the ACPI spec.

WDDT - Watchdog Descriptor Table (Table 5.6 in spec version 6.5)

> The MSCT I think we don't want to expose, as it's related to topology
> data.
> 
> Regarding RASF I would be slightly worried about the patrol scrub
> feature.  The memory map exposed to dom0 will be different from the
> native one, and there's also the interposed p2m.

Thing is - either kind of Dom0 needs to have a sufficient level of insight
into the host memory map to support memory-related RAS features. Which may
mean that RASF may only be exposed if the Dom0 kernel declares itself as
aware of the need to consider data there to refer to a separate address
space.

>> --- a/xen/arch/x86/hvm/dom0_build.c
>> +++ b/xen/arch/x86/hvm/dom0_build.c
>> @@ -1010,12 +1010,20 @@ static bool __init pvh_acpi_table_allowe
>>              return true;
>>          else
>>          {
>> +    skip:
>>              printk("Skipping table %.4s in non-ACPI non-reserved region\n",
>>                     sig);
>>              return false;
>>          }
>>      }
>>  
>> +    if ( !strncmp(sig, "OEM", 3) )
>> +    {
>> +        if ( acpi_memory_banned(address, size) )
>> +            goto skip;
>> +        return true;
>> +    }
> 
> I may have put this ahead of the loop, so that the goto label doesn't
> go backwards (which always feels weird to me).

It felt odd to me to put it first; I'm almost always hesitant to add stuff
to the front of something that's already there, due to the possible
implication of "what I add is more important than what was there before".

As to label vs goto placement: It's the other way around for me. C wants
everything else declared before use. Hence I prefer to have labels appear
before their use. I'm actually puzzled by Misra not sharing that view,
and instead having Rule 15.2 (which we haven't adopted yet afaics) to
demand the opposite (and assuming Rule 15.1 is being violated in the
first place).

>> +
> 
> I wonder if additionally we should print tables filtered to dom0 here:
> 
> if ( opt_dom0_verbose )
>     printk("Hidden ACPI Table %.4s\n", sig);
> 
> So that it's more obvious which tables are not exposed.

I, too, thought about that, but assumed it may not have been done before
for a reason. Plus it would want to be a separate change anyway, imo.

Jan



 


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