Re: [Xen-devel] [PATCH 8/9] AMD/IOMMU: enable x2APIC mode when available

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 18.06.19 at 15:40, <andrew.cooper3@xxxxxxxxxx> wrote:
> On 13/06/2019 14:27, Jan Beulich wrote:
>> @@ -1346,7 +1399,7 @@ int __init amd_iommu_init(void)
>>      /* per iommu initialization  */
>>      for_each_amd_iommu ( iommu )
>>      {
>> -        rc = amd_iommu_init_one(iommu);
>> +        rc = amd_iommu_init_one(iommu, !xt);
> 
> This logic is very subtle, and is a consequence of the bifurcated setup
> AFAICT.  I think it deserves a comment.

Will do.

>> --- a/xen/drivers/passthrough/amd/iommu_intr.c
>> +++ b/xen/drivers/passthrough/amd/iommu_intr.c
>> @@ -796,6 +796,40 @@ void* __init amd_iommu_alloc_intremap_ta
>>      return tb;
>>  }
>>  
>> +bool __init iov_supports_xt(void)
>> +{
>> +    unsigned int apic;
>> +    struct amd_iommu *iommu;
>> +
>> +    if ( !iommu_enable || !iommu_intremap || !cpu_has_cx16 )
>> +        return false;
>> +
>> +    if ( amd_iommu_prepare() )
>> +        return false;
>> +
>> +    for_each_amd_iommu ( iommu )
>> +        if ( !iommu->features.flds.ga_sup || !iommu->features.flds.xt_sup )
> 
> Why ga_sup?  I don't see anything in the manual which links xt_sup with
> ga_sup, other than the chronology of spec updated.

There is an (indirect connection), and I learned this the hard way -
I too was assuming that XTEn alone ought to be sufficient for the
IOMMU to use 128-bit IRTEs. But no, table 22 in the 3.04 doc
makes quite clear that it is GAEn alone which controls entry size.
GAMEn would also need to be set to actually do what I would have
thought should be controlled by GAEn alone.

> In particular, it is explicitly stated to be ok to use xt without ga,
> and the format of interrupts generated by the IOMMU is controlled by the
> XTEn bit.

Where did you find this? Depending how it's worded this may
deserve clarifying.

Jan



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