[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 0/9] x86: AMD x2APIC support
Despite the title this is actually all AMD IOMMU side work; all x86 side adjustments have already been carried out. If in doubt, the series is assumed to go on top of AMD/IOMMU: initialize IRQ tasklet only once [1] AMD/IOMMU: revert "amd/iommu: assign iommu devices to Xen" [2] AMD/IOMMU: don't "add" IOMMUs [3] 1: AMD/IOMMU: use bit field for extended feature register 2: AMD/IOMMU: use bit field for control register 3: AMD/IOMMU: use bit field for IRTE 4: AMD/IOMMU: introduce 128-bit IRTE non-guest-APIC IRTE format 5: AMD/IOMMU: split amd_iommu_init_one() 6: AMD/IOMMU: allow enabling with IRQ not yet set up 7: AMD/IOMMU: adjust setup of internal interrupt for x2APIC mode 8: AMD/IOMMU: enable x2APIC mode when available 9: AMD/IOMMU: correct IRTE updating Jan [1] https://lists.xenproject.org/archives/html/xen-devel/2019-05/msg02441.html [2] https://lists.xenproject.org/archives/html/xen-devel/2019-06/msg00095.html [3] https://lists.xenproject.org/archives/html/xen-devel/2019-06/msg00200.html _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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