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Re: [Xen-devel] [v3,11/41] mips: reuse asm-generic/barrier.h
- To: Will Deacon <will.deacon@xxxxxxx>, "Paul E. McKenney" <paulmck@xxxxxxxxxxxxxxxxxx>
- From: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
- Date: Fri, 15 Jan 2016 10:54:32 -0800
- Cc: linux-mips@xxxxxxxxxxxxxx, linux-ia64@xxxxxxxxxxxxxxx, "Michael S. Tsirkin" <mst@xxxxxxxxxx>, Peter Zijlstra <peterz@xxxxxxxxxxxxx>, virtualization@xxxxxxxxxxxxxxxxxxxxxxxxxx, "H. Peter Anvin" <hpa@xxxxxxxxx>, sparclinux@xxxxxxxxxxxxxxx, Ingo Molnar <mingo@xxxxxxxxxx>, linux-arch@xxxxxxxxxxxxxxx, linux-s390@xxxxxxxxxxxxxxx, Russell King - ARM Linux <linux@xxxxxxxxxxxxxxxx>, user-mode-linux-devel@xxxxxxxxxxxxxxxxxxxxx, linux-sh@xxxxxxxxxxxxxxx, Michael Ellerman <mpe@xxxxxxxxxxxxxx>, x86@xxxxxxxxxx, xen-devel@xxxxxxxxxxxxxxxxxxxx, Ingo Molnar <mingo@xxxxxxx>, linux-xtensa@xxxxxxxxxxxxxxxx, james.hogan@xxxxxxxxxx, Arnd Bergmann <arnd@xxxxxxxx>, Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>, adi-buildroot-devel@xxxxxxxxxxxxxxxxxxxxx, ddaney.cavm@xxxxxxxxx, Thomas Gleixner <tglx@xxxxxxxxxxxxx>, linux-metag@xxxxxxxxxxxxxxx, linux-arm-kernel@xxxxxxxxxxxxxxxxxxx, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, linux-kernel@xxxxxxxxxxxxxxx, Ralf Baechle <ralf@xxxxxxxxxxxxxx>, Joe Perches <joe@xxxxxxxxxxx>, linuxppc-dev@xxxxxxxxxxxxxxxx, David Miller <davem@xxxxxxxxxxxxx>
- Delivery-date: Fri, 15 Jan 2016 18:55:10 +0000
- List-id: Xen developer discussion <xen-devel.lists.xen.org>
On 01/15/2016 01:57 AM, Will Deacon wrote:
Paul,
I think you figured this out while I was sleeping, but just to confirm:
1. The MIPS64 ISA doc [1] talks about SYNC in a way that applies only
to memory accesses appearing in *program-order* before the SYNC
2. We need WRC+sync+addr to work, which means that the SYNC in P1 must
also capture the store in P0 as being "before" the barrier. Leonid
reckons it works, but his explanation [2] focussed on the address
dependency in P2 as to why this works. If that is the case (i.e.
address dependency provides global transitivity), then WRC+addr+addr
should also work (even though its not required).
No, it is not correct. There is one old design which provides access to
core (thread0 + thread1) write-buffers for threads load in advance of it
is visible to other cores. It means, that WRC+sync+addr passes because
of SYNC in write thread and register dependency inside other thread but
WRC+addr+addr may fail because other core may get a stale data.
3. It seems that WRC+addr+addr doesn't work, so I'm still suspicious
about WRC+sync+addr, because neither the architecture document or
Leonid's explanation tell me that it should be forbidden.
Will
[1] https://imgtec.com/?do-download=4302
[2] http://lkml.kernel.org/r/569565DA.2010903@xxxxxxxxxx (scroll to the end)
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- References:
- Re: [Xen-devel] [v3,11/41] mips: reuse asm-generic/barrier.h
- Re: [Xen-devel] [v3,11/41] mips: reuse asm-generic/barrier.h
- Re: [Xen-devel] [v3,11/41] mips: reuse asm-generic/barrier.h
- Re: [Xen-devel] [v3,11/41] mips: reuse asm-generic/barrier.h
- Re: [Xen-devel] [v3,11/41] mips: reuse asm-generic/barrier.h
- Re: [Xen-devel] [v3,11/41] mips: reuse asm-generic/barrier.h
- Re: [Xen-devel] [v3,11/41] mips: reuse asm-generic/barrier.h
- Re: [Xen-devel] [v3,11/41] mips: reuse asm-generic/barrier.h
- Re: [Xen-devel] [v3,11/41] mips: reuse asm-generic/barrier.h
- Re: [Xen-devel] [v3,11/41] mips: reuse asm-generic/barrier.h
- Re: [Xen-devel] [v3,11/41] mips: reuse asm-generic/barrier.h
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