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Re: [Xen-devel] [v3,11/41] mips: reuse asm-generic/barrier.h
- To: Will Deacon <will.deacon@xxxxxxx>
- From: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
- Date: Wed, 13 Jan 2016 11:02:35 -0800
- Cc: linux-mips@xxxxxxxxxxxxxx, linux-ia64@xxxxxxxxxxxxxxx, "Michael S. Tsirkin" <mst@xxxxxxxxxx>, Peter Zijlstra <peterz@xxxxxxxxxxxxx>, virtualization@xxxxxxxxxxxxxxxxxxxxxxxxxx, "H. Peter Anvin" <hpa@xxxxxxxxx>, sparclinux@xxxxxxxxxxxxxxx, Ingo Molnar <mingo@xxxxxxxxxx>, linux-arch@xxxxxxxxxxxxxxx, linux-s390@xxxxxxxxxxxxxxx, Russell King - ARM Linux <linux@xxxxxxxxxxxxxxxx>, user-mode-linux-devel@xxxxxxxxxxxxxxxxxxxxx, linux-sh@xxxxxxxxxxxxxxx, Michael Ellerman <mpe@xxxxxxxxxxxxxx>, x86@xxxxxxxxxx, xen-devel@xxxxxxxxxxxxxxxxxxxx, Ingo Molnar <mingo@xxxxxxx>, Paul McKenney <paulmck@xxxxxxxxxxxxxxxxxx>, linux-xtensa@xxxxxxxxxxxxxxxx, james.hogan@xxxxxxxxxx, Arnd Bergmann <arnd@xxxxxxxx>, Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>, adi-buildroot-devel@xxxxxxxxxxxxxxxxxxxxx, ddaney.cavm@xxxxxxxxx, Thomas Gleixner <tglx@xxxxxxxxxxxxx>, linux-metag@xxxxxxxxxxxxxxx, linux-arm-kernel@xxxxxxxxxxxxxxxxxxx, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, linux-kernel@xxxxxxxxxxxxxxx, Ralf Baechle <ralf@xxxxxxxxxxxxxx>, Joe Perches <joe@xxxxxxxxxxx>, linuxppc-dev@xxxxxxxxxxxxxxxx, David Miller <davem@xxxxxxxxxxxxx>
- Delivery-date: Wed, 13 Jan 2016 19:03:09 +0000
- List-id: Xen developer discussion <xen-devel.lists.xen.org>
On 01/13/2016 02:45 AM, Will Deacon wrote:
On Tue, Jan 12, 2016 at 12:45:14PM -0800, Leonid Yegoshin wrote:
I don't think the address dependency is enough on its own. By that
reasoning, the following variant (WRC+addr+addr) would work too:
P0:
Wx = 1
P1:
Rx == 1
<address dep>
Wy = 1
P2:
Ry == 1
<address dep>
Rx = 0
So are you saying that this is also forbidden?
Imagine that P0 and P1 are two threads that share a store buffer. What
then?
I ask HW team about it but I have a question - has it any relationship
with replacing MIPS SYNC with lightweight SYNCs (SYNC_WMB etc)? You use
any barrier or do not use it and I just voice an intention to use a more
efficient instruction instead of bold hummer (SYNC instruction). If you
don't use any barrier here then it is a different issue.
May be it has sense to return back to original issue?
- Leonid
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