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Re: [Xen-devel] [PATCH v2 04/15] xen/arm: vgic-v3: Correctly handle RAZ/WI registers

On 02/02/15 16:11, Julien Grall wrote:
> On 02/02/15 16:08, Ian Campbell wrote:
>> On Mon, 2015-02-02 at 15:59 +0000, Julien Grall wrote:
>>> Hi Ian,
>>> On 02/02/15 15:24, Ian Campbell wrote:
>>>> On Thu, 2015-01-29 at 18:25 +0000, Julien Grall wrote:
>>>>> Some of the registers are accessible via multiple size (see 
>>>>> Thoses registers are misimplemented when they should be RAZ. Only
>>>> "Those" and "incorrectly implemented".
>>>>> word-access size are currently allowed for them.
>>>>> To avoid further issues, introduce different label following the 
>>>>> access-size
>>>>> of the registers:
>>>>>     - read_as_zero_64 and write_ignore_64: Used for registers accessible
>>>>>     via a double-word.
>>>>>     - read_as_zero_32 and write_ignore_32: Used for registers accessible
>>>>>     via a word.
>>>> 5.1.3 suggests there are at least some 64-bit registers where it ought
>>>> to be possible to read the upper and lower halves independently. Don't
>>>> you need to support that?
>>> Only when the system is supporting AArch32. If the system only supports
>>> AArch64, 64-bit registers can only be read via a 64-bit access.
>>> I don't think we actually support AArch32 on the vGICv3 drivers. And we
>>> don't emulate 32-bits access on 64-bit registers.
>> It's certainly our intention in general to support arm32 guest kernels
>> on arm64, the v3 vgic may not reach that aspiration though.
> AFAICT, only the vGIC v3 is using 64-bit access. So we are fine for now.
> Linux seems to allow to build GICv3 for ARM32. I guess we should support
> it in the future.

So I was wrong, it's not possible to select GICv3 manually on ARM32. So
I will update the commit message that we only support Aarch64 for now,
therefore only 64-bit access is allowed.

Supporting Aarch32 would require more work, so it's defer until someone
care about this use case. Is it ok for you?


Julien Grall

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