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Re: [Xen-devel] [PATCH v2 04/15] xen/arm: vgic-v3: Correctly handle RAZ/WI registers

On Thu, 2015-01-29 at 18:25 +0000, Julien Grall wrote:
> Some of the registers are accessible via multiple size (see GICD_IPRIORITYR*).
> Thoses registers are misimplemented when they should be RAZ. Only

"Those" and "incorrectly implemented".

> word-access size are currently allowed for them.
> To avoid further issues, introduce different label following the access-size
> of the registers:
>     - read_as_zero_64 and write_ignore_64: Used for registers accessible
>     via a double-word.
>     - read_as_zero_32 and write_ignore_32: Used for registers accessible
>     via a word.

5.1.3 suggests there are at least some 64-bit registers where it ought
to be possible to read the upper and lower halves independently.

BTW, a reference to 5.1.3 in the changelog would be handy.


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