Re: [Xen-devel] [PATCH] x86: make IDT read-only

[Eric Northup <digitaleric@xxxxxxxxxx>]

On Wed, Apr 10, 2013 at 3:40 AM, Eric W. Biederman
<ebiederm@xxxxxxxxxxxx> wrote:
> Ingo Molnar <mingo@xxxxxxxxxx> writes:
>
>> * Eric W. Biederman <ebiederm@xxxxxxxxxxxx> wrote:
>>
>>> "H. Peter Anvin" <hpa@xxxxxxxxx> writes:
>>>
>>> > On 04/08/2013 03:43 PM, Kees Cook wrote:
>>> >> This makes the IDT unconditionally read-only. This primarily removes
>>> >> the IDT from being a target for arbitrary memory write attacks. It has
>>> >> an added benefit of also not leaking (via the "sidt" instruction) the
>>> >> kernel base offset, if it has been relocated.
>>> >>
>>> >> Signed-off-by: Kees Cook <keescook@xxxxxxxxxxxx>
>>> >> Cc: Eric Northup <digitaleric@xxxxxxxxxx>
>>> >
>>> > Also, tglx: does this interfere with your per-cpu IDT efforts?
>>>
>>> Given that we don't change any IDT entries why would anyone want a
>>> per-cpu IDT?  The cache lines should easily be shared accross all
>>> processors.
>>
>> That's true iif they are cached.
>>
>> If not then it's a remote DRAM access cache miss for all CPUs except the 
>> node that
>> holds that memory.
>>
>>> Or are there some giant NUMA machines that trigger cache misses when 
>>> accessing
>>> the IDT and the penalty for pulling the cache line across the NUMA fabric is
>>> prohibitive?
>>
>> IDT accesses for pure userspace execution are pretty rare. So we are not just
>> talking about huge NUMA machines here but about ordinary NUMA machines 
>> taking a
>> remote cache miss hit for the first IRQ or other IDT-accessing operation 
>> they do
>> after some cache-intense user-space processing.
>>
>> It's a small effect, but it exists and improving it would be
>> legitimate.
>
> If the effect is measurable I agree it is a legitimate optimization.  At
> one point there was a suggestion to make the code in the IDT vectors
> differ based on the which interrupt was registed.  While that can also
> reduce cache misses that can get hairy very quickly, and of course that
> would require read-write IDTs.

read-write IDT or GDT are fine: map them twice, once read+write, once
read-only.  Point the GDTR and IDTR at the read-only alias.

>
> My only practical concern with duplicating the IDT tables per cpu is (a)
> there are generic idt handlers that remain unduplicated reducing the
> benefit and this is essentially the same optimization as making the
> entire kernel text per cpu which last time it was examined was not an
> optimization worth making.  So I wonder if just a subset of the
> optimization is worth making.
>
> Eric

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