Re: [Xen-devel] Xen mce bugfix

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 27.02.13 at 11:37, "Liu, Jinsong" <jinsong.liu@xxxxxxxxx> wrote:
> Jan Beulich wrote:
>>>>> On 27.02.13 at 10:24, "Liu, Jinsong" <jinsong.liu@xxxxxxxxx> wrote:
>>> This work around an issue when test via xen-mceinj tools.
>>> 
>>> when inject simulated error via xen-mceinj tools,
>>> status ADDRV/MISCV bits are simulated hence there is
>>> potential risk of #GP if h/w not really support MCi_ADDR/MISC.
>>> We temporarily work around by not clean them until we have
>>> clean solution.
>> 
>> Excuse me, but - no. Changing the behavior for real MCE-s (which
>> you added) for the benefit of fixing injection is a no-go IMO. Or
>> are you telling us that after all that earlier change of yours is not
>> really necessary (in which case we could as well revert it).
>> 
>> Jan
>> 
> 
> The reason of the former patch to clear MCi_ADDR/MISC is that it's 
> recommended by Intel SDM:
>               LOG MCA REGISTER:
>               SAVE IA32_MCi_STATUS;
>               If MISCV in IA32_MCi_STATUS
>               THEN
>                       SAVE IA32_MCi_MISC;
>               FI;
>               IF ADDRV in IA32_MCi_STATUS
>               THEN
>                       SAVE IA32_MCi_ADDR;
>               FI;
>               IF CLEAR_MC_BANK = TRUE
>               THEN
>                       SET all 0 to IA32_MCi_STATUS;
>               If MISCV in IA32_MCi_STATUS
>               THEN
>                       SET all 0 to IA32_MCi_MISC;
>               FI;
>               IF ADDRV in IA32_MCi_STATUS
>               THEN
>                       SET all 0 to IA32_MCi_ADDR;
>               FI;
> 
> For Xen mce, it's meaningful to read MCi_ADDR/MISC only when real error 
> occur (which indicated by MCi_STATUS), so only clear MCi_STATUS at mce 
> handler is an acceptable work around -- after all, to read MCi_ADDR/MISC is 
> pointless if MCi_STATUS is 0.

So then what - revert your original patch (and ignore the SDM)?
I'm not in favor of this...

Jan


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