[Xen-devel] Xen mce bugfix

["Liu, Jinsong" <jinsong.liu@xxxxxxxxx>]

This work around an issue when test via xen-mceinj tools.

when inject simulated error via xen-mceinj tools,
status ADDRV/MISCV bits are simulated hence there is
potential risk of #GP if h/w not really support MCi_ADDR/MISC.
We temporarily work around by not clean them until we have
clean solution.

Reported-by: Ren Yongjie <yongjie.ren@xxxxxxxxx>
Singed-off-by: Liu Jinsong <jinsong.liu@xxxxxxxxx>

diff -r e84a79d11d7a xen/arch/x86/cpu/mcheck/mce.c
--- a/xen/arch/x86/cpu/mcheck/mce.c     Thu Nov 01 01:41:03 2012 +0800
+++ b/xen/arch/x86/cpu/mcheck/mce.c     Thu Feb 28 00:34:22 2013 +0800
@@ -144,10 +144,19 @@
 
     status = mca_rdmsr(MSR_IA32_MCx_STATUS(banknum));
 
+/*
+ * TODO: when inject simulated error via xen-mceinj tools,
+ * status ADDRV/MISCV bits are simulated hence there is
+ * potential risk of #GP if h/w not really support MCi_ADDR/MISC.
+ * We temporary work around by not clean them until we have
+ * clean solution.
+ */
+#if 0
     if (status & MCi_STATUS_ADDRV)
         mca_wrmsr(MSR_IA32_MCx_ADDR(banknum), 0x0ULL);
     if (status & MCi_STATUS_MISCV)
         mca_wrmsr(MSR_IA32_MCx_MISC(banknum), 0x0ULL);
+#endif
 
     mca_wrmsr(MSR_IA32_MCx_STATUS(banknum), 0x0ULL);
 }

Attachment: xen-mce-bugfix.patch
Description: xen-mce-bugfix.patch

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