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Re: [Xen-devel] [PATCH] AMD: Enable WC+ memory type on family 10 processors
On 17/01/13 18:44, Boris Ostrovsky wrote:
# HG changeset patch
# User Boris Ostrovsky <boris.ostrovsky@xxxxxxx>
# Date 1358429914 18000
# Node ID 1963e398ba0f5dd61818d92400c7b07a32f6da4b
# Parent b6195e277da52129d5d79f29ccac0e7290643e37
AMD: Enable WC+ memory type on family 10 processors
In some cases BIOS may not enable WC+ memory type on family 10 processors,
instead converting what would be WC+ memory to CD type. On guests using
nested pages this could result in performance degradation. This patch
enables WC+.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxx>
diff -r b6195e277da5 -r 1963e398ba0f xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c Wed Jan 16 14:15:44 2013 +0000
+++ b/xen/arch/x86/cpu/amd.c Thu Jan 17 08:38:34 2013 -0500
@@ -495,6 +495,18 @@ static void __devinit init_amd(struct cp
set_bit(X86_FEATURE_ARAT, c->x86_capability);
/*
+ * On family 10h BIOS may not have properly enabled WC+ support, causing
+ * it to be converted to CD memtype. This may result in performance
+ * degradation for certain nested-paging guests. Prevent this conversion
+ * by enabling WC+ support through MSRC001_1024A[24] = 0
Pedantic: The MSR number seems to have a surplus 4 in it...
--
Mats
+ */
+ if (c->x86 == 0x10) {
+ rdmsr_safe(0xc001102a, value);
+ value &= ~(1ULL << 24);
+ wrmsr_safe(0xc001102a, value);
+ }
+
+ /*
* Prior to Family 0x14, perf counters are not reset during warm reboot.
* We have to reset them manually.
*/
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