[PATCH] arm/entry: set x0 before cache maintenance.

[Jianyong Wu <jianyong.wu@xxxxxxx>]

There is a long standing issue in entry code of arm that x0 is not
set before using it in clean_and_invalidate_dcache_range. This error
can be caught by kvm and result in core dump.
Here, x0 is set to the base address of dtb before cache maintain.

Jira: ENTOS-2050
Signed-off-by: Jianyong Wu <jianyong.wu@xxxxxxx>
Change-Id: Ia81f5c65c19a33b7a640efcd4d3117f61c59dd28
---
 plat/kvm/arm/entry64.S | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/plat/kvm/arm/entry64.S b/plat/kvm/arm/entry64.S
index c4de334..0526ae8 100644
--- a/plat/kvm/arm/entry64.S
+++ b/plat/kvm/arm/entry64.S
@@ -92,6 +92,12 @@ ENTRY(_libkvmplat_entry)
        add x27, x26, x17
        add x27, x27, #__STACK_SIZE
        sub x1, x27, x25
+
+       /*
+        * set x0 to the location stores dtb as the base address of the
+        * memory range to be cache maintained
+        */
+       ldr x0, =_dtb
        bl clean_and_invalidate_dcache_range
 
        /* Disable the MMU and D-Cache. */
-- 
2.17.1