Re: [Xen-ia64-devel] [PATCH] add support for hvm live migration

[Kouya Shimura <kouya@xxxxxxxxxxxxxx>]

The fault address must be on a TLB when a dirty bit fault is generated.
So I believe that a tlb miss of tpa never happen at this point
as long as IVT is mapped by a TR.

-- Kouya

Tristan Gingold writes:
> On Tue, Feb 12, 2008 at 05:54:39PM +0900, Kouya Shimura wrote:
> Content-Description: message body text
> > Hi,
> > 
> > This is a naive implementation of log dirty mode for HVM.
> [...]
> > diff -r 9203ee23e724 xen/arch/ia64/vmx/vmx_ivt.S
> > --- a/xen/arch/ia64/vmx/vmx_ivt.S   Thu Feb 07 11:08:49 2008 -0700
> > +++ b/xen/arch/ia64/vmx/vmx_ivt.S   Tue Feb 12 16:37:32 2008 +0900
> > @@ -433,8 +433,27 @@ END(vmx_dkey_miss)
> >  
> > /////////////////////////////////////////////////////////////////////////////////////////
> >  // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
> >  ENTRY(vmx_dirty_bit)
> > -    VMX_DBG_FAULT(8)
> > -    VMX_REFLECT(8)
> > +    mov r29=cr.ipsr
> > +    mov r31=pr
> > +    ;;
> > +    tbit.z p6,p0=r29,IA64_PSR_VM_BIT
> > +    mov r19=8
> > +(p6)br.spnt.many dispatch_to_fault_handler
> > +    mov r19=cr.ifa
> > +    movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET
> > +    ;;
> > +    tpa r19=r19
> 
> Can't this tpa generate a nested tlb miss ?
> 
> Tristan.

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