RE: [Xen-ia64-devel] [Patch] Speculative Load/Store to IO memory

["Xu, Anthony" <anthony.xu@xxxxxxxxx>]

> Akio Takebe 
>Sent: 2007年5月18日 11:43
>To: Xu, Anthony; xen-ia64-devel
>Cc: Akio Takebe
>Subject: RE: [Xen-ia64-devel] [Patch] Speculative Load/Store to IO memory
>No, this guest work on virtual mode. My patch is for virtual mode.
>This address is 0xa0000000fee00018.
>When we found the isssue, arguments of mmio_access() are
> (f000000007980000, fee00018, f000000007987d80, 4, 4, 1),
>so I think it is un-cachable.

Windows ld.s on un-cacheable page, this breaks ia64 spec.
Can you dump the code segment and related information such as register value 
and 
tlb entres and the windows version you are using?

I can send this to Intel windows team.



>
>>
>>If it is a un-cacheable address,
>>According to spec, the behavior of ld.s on un-cacheable page is undefined.
>>We can set psr.ed directly.
>>
>Is cheking ma=4 better?

This is better.
We still need to find out the behavior of ld.s on cacheable IO page.


>
>>If it is a cacheable address and it is IO address.
>>I don't know the real behavior on native machine.
>>So we need to get the real behavior first, then decide how to emulate it.
>>I'm asking some exports, hope I can get the answer.
>>
>Thanks.
>This issue is difficult to reproduce,
>because we don't know step to reproduce.

Forget it.
I'll try to get the answer.

Thanks,
Anthony

_______________________________________________
Xen-ia64-devel mailing list
Xen-ia64-devel@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-ia64-devel