[PATCH v4 02/42] xen/riscv: address violation of MISRA C Rule 20.12 in csr_write64()

[Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>]

csr_write64() uses its csr parameter both as an operand of ## (to form the
name of the CSR holding the upper half on RV32) and in ordinary,
macro-expanded context. As the CSR_* constants are macros themselves, this
violates MISRA C Rule 20.12.

Make csr_write64() take the CSR name without the CSR_ prefix and paste the
prefix as well, so that the parameter is used as an operand of ## only.

While at it, drop the (void) of the upper half CSR on RV64: it generated
no code and only made the build fail if CSR_<name>H wasn't defined, while
a pure 64-bit environment has no need for the ...H constants.

No functional change.

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
---
Changes in v4:
 - New patch.
---
---
 xen/arch/riscv/include/asm/csr.h | 16 ++++++----------
 xen/arch/riscv/time.c            |  4 ++--
 2 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/csr.h
index a805f7ed0ba1..3cf8e1857ce2 100644
--- a/xen/arch/riscv/include/asm/csr.h
+++ b/xen/arch/riscv/include/asm/csr.h
@@ -33,18 +33,14 @@
 })
 
 #ifdef CONFIG_RISCV_32
-#define csr_write64(csr, val)       \
-({                                  \
-    uint64_t v_ = (val);            \
-    csr_write(csr, v_);             \
-    csr_write(csr ## H, v_ >> 32);  \
+#define csr_write64(name, val)              \
+({                                          \
+    uint64_t v_ = (val);                    \
+    csr_write(CSR_ ## name, v_);            \
+    csr_write(CSR_ ## name ## H, v_ >> 32); \
 })
 #else
-#define csr_write64(csr, val)       \
-({                                  \
-    csr_write(csr, val);            \
-    (void)csr ## H;                 \
-})
+#define csr_write64(name, val) csr_write(CSR_ ## name, val)
 #endif
 
 #define csr_swap(csr, val)                                      \
diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c
index 782d9cd450f3..97ebe402ae41 100644
--- a/xen/arch/riscv/time.c
+++ b/xen/arch/riscv/time.c
@@ -15,7 +15,7 @@ uint64_t __ro_after_init boot_clock_cycles;
 
 static int cf_check sstc_set_xen_timer(uint64_t deadline)
 {
-    csr_write64(CSR_STIMECMP, deadline);
+    csr_write64(STIMECMP, deadline);
 
     return 0;
 }
@@ -103,6 +103,6 @@ void __init preinit_xen_time(void)
          * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to
          * ~0.
          */
-        csr_write64(CSR_VSTIMECMP, ~0);
+        csr_write64(VSTIMECMP, ~0);
     }
 }
-- 
2.56.1