[PATCH RFC] x86/hvm: Disallow modifying the APIC_ID register

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

The APIC_ID register is strictly read-only in x2APIC mode.  In xAPIC mode,
both Intel and AMD document the read-only-ness as being implementation
dependent.

In practice, for Intel it's read-only on any x2APIC-capable hardware (Nehalem
and later, so almost two decades now).  For AMD, the register is writeable but
doing so trucates the 32bit x2APIC ID, so in practice nothing (not even the
firmware) does modify it.

Just as we disallow changing the LAPIC base for ease of supporting APIC
virtualisation extentions, ignore guest writes to the APIC_ID in xAPIC mode.

Note, this still allows the toolstack to configure APIC IDs, for migration and
topology reasons.

Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
CC: Jan Beulich <jbeulich@xxxxxxxx>
CC: Roger Pau Monné <roger@xxxxxxxxxxxxxx>
CC: Teddy Astie <teddy.astie@xxxxxxxxxx>
CC: Jason Andryuk <jason.andryuk@xxxxxxx>
CC: Denis Mukhin <dmukhin@xxxxxxxx>
CC: Ross Lagerwall <ross.lagerwall@xxxxxxxxxx>

This patch is from 2019.  I apparently never got as far as sending it...

This is even lower risk than disallowing changing the xAPIC MMIO window.
There's been no comment or issue with that restriction, which has been in
place since 2018.

It is however RFC.

 * Without this APIC_ID restriction, we need to modify the logical id table in
   response to changes, including disabling AVIC domain-wide if the guest sets
   a layout which can't be expressed.  Intel have gained a similar table with
   their IPI Virt capability on SPR and later.

 * Both Intel and AMD allow writes to the APIC_ID to be accelerated, and give
   a trap VMExit after the backing page has been updated.  So if we're going
   to enforce this restriction then we need the VMExit to undo the
   modification.
---
 xen/arch/x86/hvm/vlapic.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
index 6698779e227c..358fdd4baf92 100644
--- a/xen/arch/x86/hvm/vlapic.c
+++ b/xen/arch/x86/hvm/vlapic.c
@@ -795,10 +795,6 @@ void vlapic_reg_write(struct vcpu *v, unsigned int reg, 
uint32_t val)
 
     switch ( reg )
     {
-    case APIC_ID:
-        vlapic_set_reg(vlapic, APIC_ID, val);
-        break;
-
     case APIC_ESR:
         val = xchg(&vlapic->hw.pending_esr, 0);
         vlapic_set_reg(vlapic, APIC_ESR, val);

base-commit: c4a09c112c391ffc1aea33afff49ffb28156fbdb
-- 
2.39.5