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Re: [PATCH v5 1/3] xen/riscv: always preset A/D bits in G-stage PTEs


  • To: Baptiste Le Duc <baptiste.le-duc@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
  • From: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
  • Date: Wed, 7 Oct 2026 10:30:59 +0200
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  • Delivery-date: Wed, 07 Oct 2026 08:31:05 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>



On 10/7/26 10:21 AM, Baptiste Le Duc wrote:
On 10/7/26 00:50, Teddy Astie wrote:
Le 05/10/2026 à 18:02, Baptiste Le Duc a écrit :
A RISC-V implementation can manage the PTE A/D bits in one of two ways:
     1) Update the 'A' and 'D' PTE bits in hardware (ratified as Svadu).
     2) Generate a page fault when 'A' and/or 'D' is clear, so that software
        can set them (ratified as Svade).

p2m_set_pte_flags() presets A/D in G-stage PTEs only when the device tree advertises Svade. Platforms that use scheme (2) without advertising Svade, such as the HiFive Premier P550, then hit guest-page faults that Xen does
not handle.

I second what Jan said (this is likely a firmware bug, given that the enumerated behavior is not consistent with the specification, as existence of Svadu/Svade alters observable behavior).

Thanks, agreed on both points.

I'll reword the commit message: it shouldn't imply that Svade in the DT means faults will occur, since with Svadu also present that depends on henvcfg.ADUE.

On the firmware-bug point: I don't think the P550 is really inconsistent with the spec. Svade and Svadu didn't exist when the P550 core was designed. They were only ratified later, to name the two behaviors that already existed in the wild. Before that, the privileged spec just allowed either: hardware updating A/D, or raising a page fault. The P550 implements the second, and there was no extension it could advertise for it. Therefore, the DT lacks svade because the extension didn't exist when the platform description was written, not because the vendor misdescribed anything.

I agree that, where Svadu is available, Xen should ideally configure a consistent scheme (ADUE=1) and use ADUE=0 only for specific needs such as dirty tracking. But Xen doesn't support Svadu today, so that is a separate piece of work which I'd prefer to do later.

It would be nice to have such option to configure ADUE bit but IIRC it could be configured only in M-mode (so OpenSBI and OpenSBI really set ADUE to 1 when Svadu is available) so we will need some kind of new SBI call to do that as we are working in HS-mode and can't change ADUE bit.

So IMO we don't really need that for now until we really will start to use A/D bits for Xen purpose. For me, at the moment, it is more then enough just to have them always set.

~ Oleksii




 


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