Re: [PATCH v3 11/39] xen/riscv: implement vCPU context switching

[Baptiste Le Duc <baptiste.le-duc@xxxxxxxxxx>]

On 2026-10-07 10:04:12+02:00, Jan Beulich wrote:
> On 06.10.2026 18:50, Baptiste Le Duc wrote:
> 
> >> Implement context_switch() and the helpers it needs: save/restore of
> 
> First: None of the reply context above is relevant in your reply. Why
> did you keep it? As indicated before, this way you make every reader
> scroll through many lines, until they would finally find the first
> piece of the actual reply. (I've deliberately kept it all, to show
> the percentage of the overall reply that this occupied.)
> 
Yes sorry, I thought b4 would have trimmed for me. I would be careful
about that in next replies.
> >> --- a/xen/arch/riscv/include/asm/csr.h
> > This violates Misra 20.12 rule (docs/misra/rules.rst) as we use macro
> > parameter `csr` as an operand of ##, while it could be expanded as a
> > macro (e.g. csr_read64(CSR_HENVCFG)).
> 
> Yes. But: You say nothing as to a possible (and plausible) different
> way of coding this. Imo the best way to deal with this is by a
> deviation (iirc we already have a few), yet I don't think we're going
> to add deviations for RISC-V until we actually are about to routinely
> scan the code.
I didn't propose anything because I didn't have any other way to code
this. Concerning the fact to not add deviation for RISC-V I agree that
it doesn't make too much sense for the moment.
> 
> Jan