Re: [PATCH v2 1/6] xen/riscv: fix Svade/Svadu A/D bit handling

[Baptiste Le Duc <baptiste.le-duc@xxxxxxxxxx>]

On 2026-09-22 17:14:23+02:00, Oleksii Kurochko wrote:
> On 9/22/26 11:17 AM, Baptiste Le Duc wrote:
> 
> > On 2026-09-22 08:24 +0200, Jan Beulich wrote:
> > Ok, now I understand, thanks. I'll fix it in next round.
> > We don't know but based on [1] and my commit message, if neither
> > Svade nor Svadu are present in DT then it is technically unknown whether
> > the platform uses Svade or Svade. Hypervisor may then assume Svade to be
> > present and enabled or it can discover based on mvendorid, marchid, and
> > mimpid. For this patch, I choose to have the Hypervisor assumed Svade.
> 
> Can hypervisor really access this regs?
No it can't as they are M-mode only, it's why I choose to have the Hypervisor 
assumed Svade.
> 
> ~ Oleksii