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Re: [PATCH 5/5] xen/riscv: add SFENCE.VMA after enabling paging
- To: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>, Baptiste Le Duc <baptiste.le-duc@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Fri, 28 Aug 2026 09:13:28 +0200
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- Cc: zhangzheng@xxxxxxxxxxx, Alistair Francis <alistair.francis@xxxxxxx>, Connor Davis <connojdavis@xxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Anthony PERARD <anthony.perard@xxxxxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Julien Grall <julien@xxxxxxx>, Roger Pau Monné <roger@xxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- Delivery-date: Fri, 28 Aug 2026 07:13:38 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 27.08.2026 18:53, Oleksii Kurochko wrote:
> On 8/27/26 5:33 PM, Baptiste Le Duc wrote:
>> --- a/xen/arch/riscv/riscv64/head.S
>> +++ b/xen/arch/riscv/riscv64/head.S
>> @@ -98,6 +98,7 @@ FUNC(turn_on_mmu)
>> srli t1, t1, PAGE_SHIFT
>> or t1, t1, t0
>> csrw CSR_SATP, t1
>
> ... ASID isn't used as we are in Bare mode.
>
> What am I missing?
>
>> + sfence.vma
>
> The one thing which possibly matters here, and could explain why
> sfence.vma is needed, is:
> ```
> Implementations with virtual memory are permitted to perform address
> translations speculatively and earlier than required by an explicit
> memory access, and are permitted to cache them in address translation
> cache structures—including possibly caching the identity mappings from
> effective address to physical address used in Bare translation modes and
> M-mode.
> ```
>
> So the TLB could potentially be populated with identity mappings, and I
> agree that it would be better to flush those.
First: Does (or at least may) the TLB come into play in Bare mode? If not,
there's nothing to invalidate. If so, the next question would be whether
it's indeed ASID 0 which is (or again may be) used in such TLB entries.
Jan
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