Re: [PATCH 00/17] Q35 initial support for HVM guests

[Alexey G <x1917x@xxxxxxxxx>]

On Mon, 4 May 2026 12:45:23 +0200
Jan Beulich <jbeulich@xxxxxxxx> wrote:

>> Why do you need multi bus support to expose PCIe capabilities?  I'm
>> not seeing the relation between those two.  You could still expose a
>> single bus on the MCFG table.
>
>Can a valid PCIe topology be expressed with just bus 0? If an endpoint
>to be handed to a guest isn't root complex integrated, would it be
>valid to make it appear so by putting it on bus 0?

No, unfortunately, it will fail at least under Windows' pci.sys
driver. Unless they changed something in the past years. To place an
endpoint device to bus 0, we need to emulate that it's a
chipset-integrated device by trapping its PCIe Capabilities reads.

I found an old pci.sys + .pdb symbols which I used for debugging back
in 2017 and, if I remember correctly, the failing function was 
`ExpressValidateFabricTopology()`.