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Re: [PATCH 00/17] Q35 initial support for HVM guests
- To: Roger Pau Monné <roger.pau@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Mon, 4 May 2026 12:45:23 +0200
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- Cc: xen-devel@xxxxxxxxxxxxxxxxxxxx, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Anthony PERARD <anthony.perard@xxxxxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Julien Grall <julien@xxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Juergen Gross <jgross@xxxxxxxx>, Thierry Escande <thierry.escande@xxxxxxxxxx>
- Delivery-date: Mon, 04 May 2026 10:45:25 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 28.04.2026 09:48, Roger Pau Monné wrote:
> On Fri, Mar 13, 2026 at 04:35:01PM +0000, Thierry Escande wrote:
>> This series introduces initial Q35 chipset support for HVM guests, based on
>> the
>> patchset at [1] by Alexey Gerasimenko.
>>
>> Basic support means that this patchset allows to start an HVM guest that
>> emulates a Q35 chipset via Qemu and implements access to PCIe extended
>> configuration space for such devices emulated by Qemu.
>>
>> Support for PCIe device passthrough is not implemented yet. This is planned
>> but
>> implies modifications in the hypervisor and the firmwares, mainly for the
>> support of multiple PCI buses.
>
> Why do you need multi bus support to expose PCIe capabilities? I'm
> not seeing the relation between those two. You could still expose a
> single bus on the MCFG table.
Can a valid PCIe topology be expressed with just bus 0? If an endpoint
to be handed to a guest isn't root complex integrated, would it be valid
to make it appear so by putting it on bus 0?
Jan
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