Re: [PATCH v1 1/3] xen/riscv: introduce struct arch_vcpu

[Jan Beulich <jbeulich@xxxxxxxx>]

On 02.02.2026 13:57, Oleksii Kurochko wrote:
> --- a/xen/arch/riscv/include/asm/domain.h
> +++ b/xen/arch/riscv/include/asm/domain.h
> @@ -24,6 +24,55 @@ struct arch_vcpu_io {
>  
>  struct arch_vcpu {
>      struct vcpu_vmid vmid;

Nit: This being already here contradicts the title saying "introduce".

> +
> +    /*
> +     * Callee saved registers for Xen's state used to switch from
> +     * prev's stack to the next's stack during context switch.
> +     */
> +    struct
> +    {
> +        register_t s0;
> +        register_t s1;
> +        register_t s2;
> +        register_t s3;
> +        register_t s4;
> +        register_t s5;
> +        register_t s6;
> +        register_t s7;
> +        register_t s8;
> +        register_t s9;
> +        register_t s10;
> +        register_t s11;
> +        register_t sp;
> +        register_t ra;
> +    } xen_saved_context;
> +
> +    register_t hedeleg;
> +    register_t hideleg;
> +    register_t hvip;
> +    register_t hip;
> +    register_t hie;
> +    register_t hgeie;
> +    register_t henvcfg;
> +    register_t hcounteren;
> +    register_t htimedelta;
> +    register_t htval;
> +    register_t htinst;
> +    register_t hstateen0;
> +#ifdef CONFIG_RISCV_32
> +    register_t henvcfgh;
> +    register_t htimedeltah;
> +#endif

When you add these right away, any reason other high-half registers aren't added
as well? HVIP (above) and VSIE / VSIP at the very least have such counterparts,
iirc.

> +    register_t vsstatus;
> +    register_t vsip;
> +    register_t vsie;
> +    register_t vstvec;
> +    register_t vsscratch;
> +    register_t vscause;
> +    register_t vstval;
> +    register_t vsatp;
> +    register_t vsepc;
>  };

What I'm generally concerned of: With the registers all being put here in one 
go,
without any of them actually being used in this patch, it'll likely be harder to
track that they're saved / restored / initialized correctly (once uses appear).

Jan