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Re: [PATCH for-4.21??? 1/3] x86/vLAPIC: add indirection to LVT handling
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Wed, 8 Oct 2025 16:05:39 +0200
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- Cc: Roger Pau Monné <roger.pau@xxxxxxxxxx>, Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>, Grygorii Strashko <grygorii_strashko@xxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Wed, 08 Oct 2025 14:05:47 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 08.10.2025 15:04, Andrew Cooper wrote:
> On 08/10/2025 1:08 pm, Jan Beulich wrote:
>> In preparation to add support for the CMCI LVT, which is discontiguous to
>> the other LVTs, add a level of indirection.
>
> It's not the only extra LVT.
>
> AMD have Extended LVTs, which are necessary if we want to get virt-PMU
> working.
>
> https://sandpile.org/x86/apic.htm is a recent addition which covers all
> of this.
Hmm, yes, but these will need taking care of separately anyway.
>> Rename the prior
>> vlapic_lvt_mask[] while doing so (as subsequently a 2nd array will want
>> adding, for use by guest_wrmsr_x2apic()).
>>
>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
>
> I'm afraid this introduces a vulnerability.
>
> APIC_LVR is a toolstack-provided value. Nothing bounds checks the
> MAX_LVT value in it AFAICT, and previously this did not matter (from a
> security point of view at least) because the loop bounds were constant.
Oh, right, I should have thought of that. As you don't suggest anything,
I'm going to simply add a check that the incoming value matches the one
that's there already. There will still be a quirk due to MCG_CAP and
APIC registers being loaded separately, with no defined ordering between
them. Within our current infrastructure I don't really see how to deal
with this kind of inter-dependency.
Jan
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