Re: [PATCH v2 1/2] xen/mpu: Map early uart when earlyprintk on

[Ayan Kumar Halder <ayankuma@xxxxxxx>]

Hi Julien and Luca,

(Luca, I will respond to your other comment here)

On 03/12/2024 13:50, Julien Grall wrote:
> On 03/12/2024 13:34, Ayan Kumar Halder wrote:
> > On 02/12/2024 20:53, Julien Grall wrote:
> > > Hi Ayan,
> > Hi Julien,
> > > On 27/11/2024 18:39, Ayan Kumar Halder wrote:
> > > > CONFIG_EARLY_UART_SIZE is introduced to let user provide physical 
> > > > size of
> > > > early UART. Unlike MMU where we map a page in the virtual address 
> > > > space,
> > > > here we need to know the exact physical size to be mapped.
> > > > As VA == PA in case of MPU, the memory layout follows exactly the 
> > > > hardware
> > > > configuration. As a consequence, we set EARLY_UART_VIRTUAL_ADDRESS 
> > > > as physical
> > > > address.
> > > >
> > > > EARLY_UART_BASE_ADDRESS and EARLY_UART_SIZE should be aligned to 
> > > > the minimum
> > > > size of MPU region (ie 64 bits) as per the hardware restrictions. 
> > > > Refer ARM
> > > > DDI 0600A.d ID120821 A1.3 "A minimum protection region size of 64 
> > > > bytes.".
> > > > UART is mapped as nGnRE region (as specified by ATTR=100 , refer 
> > > > G1.3.13,
> > > > MAIR_EL2, "---0100 Device memory nGnRE") and Doc ID - 
> > > > 102670_0101_02_en
> > > I can't find the Doc you point online. Do you have a link?
> > https://developer.arm.com/documentation/102670/0101 - Cortex-R82 
> > processor TRM
> Thanks. But why are you quoting the Cortex-R82 TRM? 
> This code is meant to work on any Armv8-R processor.
You mean Armv8-R AArch64 processor.

Actually, I was looking for a reference to tell me if UART is to be 
mapped as a nGnRE or nGnRnE. Table 4-3 mentions that nGnRE corresponds 
to the device memory. So, I used this. I assumed that this behavior will 
apply to all Armv8-R AArch64 processors as it did not mention anything 
specific about R82.
To address Luca's comment

>>"on Zephyr, the pl011 is mapped with nGnRnE".

I don't really have a good reason whether we should map it as nGnRnE or 
nGnRE other than what I have mentioned before (ie nGnRE corresponds to 
device memory). I am happy to change it to make it consistent with 
Zephyr and Linux 
(https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/include/asm/mpu.h?h=v6.13-rc1#n67 
, this is Armv8-R **AArch32** ).
Let me know which one you think is correct.

Other comment from Luca

>>"Anyway, changing that to 0x01 (ATTR=0 EN=1) is giving me a weird 
issue in my branch:"
This is due to 
https://gitlab.com/xen-project/people/lucafancellu/xen/-/commit/4ec46883b1dffcbafd86c32732d1267102696d84 
, |ioremap_cache() in arm/mpu/mm.c . This can be fixed if we choose nGnRnE.|
|- Ayan|