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Re: [PATCH v3 7/9] xen/riscv: introduce and init SBI RFENCE extension
- To: oleksii.kurochko@xxxxxxxxx
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Wed, 7 Aug 2024 13:37:27 +0200
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- Cc: Alistair Francis <alistair.francis@xxxxxxx>, Bob Eshleman <bobbyeshleman@xxxxxxxxx>, Connor Davis <connojdavis@xxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- Delivery-date: Wed, 07 Aug 2024 11:37:35 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 07.08.2024 13:29, oleksii.kurochko@xxxxxxxxx wrote:
> On Tue, 2024-07-30 at 11:17 +0200, Jan Beulich wrote:
>>>>> +
>>>>> +static void sbi_cpumask_to_hartmask(const struct cpumask
>>>>> *cmask,
>>>>> + struct cpumask *hmask)
>>>>
>>>> I doubt it is valud to re-use struct cpumask for hart maps.
>>> Why not? Would it be better to use unsigned long *hmask?
>>
>> It's not only better, but imo a requirement. Unless there's a
>> guarantee
>> by the spec that hart IDs for any subset of harts are sequential and
>> starting from 0, you just can't assume they fall in the [0,NR_CPUS)
>> or
>> really [0,nr_cpu_ids) range. Yet without that you simply can't
>> (ab)use
>> struct cpumask (and btw it wants to be cpumask_t everywhere).
>>
>> You may want to take a look at struct physid_mask that we have on x86
>> for the equivalent purpose.
> Could you please explain me why factor 4 is used in defintion of
> MAX_APICS and why 256 ( is it a maximum number of APIC IDs can be
> supported in the system? ):
> #define MAX_APICS MAX(256, 4 * NR_CPUS)
Both numbers are pretty arbitrary, I suppose. APIC IDs need not be
contiguous, which is what the multiplication by 4 is trying to cover
for. Plus on old (non-x2APIC) systems APIC IDs are only 8 bits wide,
and allowing for all possible values in that case is cheap enough -
hence the 256.
Jan
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