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Re: [PATCH] x86/features: More AMD features
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Wed, 20 Mar 2024 09:12:03 +0100
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- Cc: Roger Pau Monné <roger.pau@xxxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Wed, 20 Mar 2024 08:12:07 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 19.03.2024 18:40, Andrew Cooper wrote:
> It occurs to me that I need this hunk too.
>
> diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
> index 25d329ce486f..bf3f9ec01e6e 100755
> --- a/xen/tools/gen-cpuid.py
> +++ b/xen/tools/gen-cpuid.py
> @@ -329,6 +329,10 @@ def crunch_numbers(state):
> # In principle the TSXLDTRK insns could also be considered
> independent.
> RTM: [TSXLDTRK],
>
> + # Enhanced Predictive Store-Forwarding is a informational note
> on top
> + # of PSF.
> + PSFD: [EPSF],
> +
> # The ARCH_CAPS CPUID bit enumerates the availability of the
> whole register.
> ARCH_CAPS: list(range(RDCL_NO, RDCL_NO + 64)),
>
>
> To cause EPSF to disappear properly when levelling.
What exactly is wrong with exposing EPSF when PSFD is not there? (The PPR
I'm looking at has no mention of what exactly the bit means, and hence
whether e.g. it indicates PSFD can be avoided in certain use cases.) When
leveling across a pool, EPSF may need hiding, yes, but that would need to
be a result of admin activity, not by introducing a fake dependency. Just
consider a pool with PSFD supported everywhere, but not EPSF: The admin
would then still need to take action to make sure EPSF is uniformly
invisible to guests.
Jan
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