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Re: [PATCH] x86/features: More AMD features


  • To: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • Date: Tue, 19 Mar 2024 17:40:03 +0000
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  • Cc: Jan Beulich <JBeulich@xxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • Delivery-date: Tue, 19 Mar 2024 17:40:17 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 18/03/2024 6:13 pm, Andrew Cooper wrote:
> All of these are informational and require no further logic changes in Xen to
> support.
>
> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> ---
> CC: Jan Beulich <JBeulich@xxxxxxxx>
> CC: Roger Pau Monné <roger.pau@xxxxxxxxxx>
>
> I'm not sure about FSRSC as a name, but it definitely beats AMD's longhand
> name of FAST_REP_SCASB.
> ---
>  tools/misc/xen-cpuid.c                      | 5 +++++
>  xen/include/public/arch-x86/cpufeatureset.h | 8 ++++++++
>  2 files changed, 13 insertions(+)
>
> diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
> index 51efbff579e6..b562ee839d38 100644
> --- a/tools/misc/xen-cpuid.c
> +++ b/tools/misc/xen-cpuid.c
> @@ -91,6 +91,7 @@ static const char *const str_e1c[32] =
>      [24] = "perfctr-nb", /* [25] */
>      [26] = "dbx",        [27] = "perftsc",
>      [28] = "pcx-l2i",    [29] = "monitorx",
> +    [30] = "dbext2",
>  };
>  
>  static const char *const str_7b0[32] =
> @@ -199,11 +200,15 @@ static const char *const str_7a1[32] =
>  
>  static const char *const str_e21a[32] =
>  {
> +    [ 0] = "no-nest-bp",    [ 1] = "fs-gs-ns",
>      [ 2] = "lfence+",
>      [ 6] = "nscb",
>      [ 8] = "auto-ibrs",
> +    [10] = "amd-fsrs",      [11] = "amd-fsrc",
>  
>      /* 16 */                [17] = "cpuid-user-dis",
> +    [18] = "epsf",          [19] = "fsrsc",

It occurs to me that I need this hunk too.

diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index 25d329ce486f..bf3f9ec01e6e 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -329,6 +329,10 @@ def crunch_numbers(state):
         # In principle the TSXLDTRK insns could also be considered
independent.
         RTM: [TSXLDTRK],
 
+        # Enhanced Predictive Store-Forwarding is a informational note
on top
+        # of PSF.
+        PSFD: [EPSF],
+
         # The ARCH_CAPS CPUID bit enumerates the availability of the
whole register.
         ARCH_CAPS: list(range(RDCL_NO, RDCL_NO + 64)),
 

To cause EPSF to disappear properly when levelling.

~Andrew



 


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