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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v5 12/23] xen/riscv: introduce io.h
On Fri, 2024-03-08 at 08:26 +0100, Jan Beulich wrote:
> On 07.03.2024 21:54, Oleksii wrote:
> > On Thu, 2024-03-07 at 21:49 +0100, Oleksii wrote:
> > > On Thu, 2024-03-07 at 18:14 +0100, Jan Beulich wrote:
> > > > For plain writes it should at least be "=Qo" then, yes.
> > > Constraints Q is a machine specific constraint, and I am not sure
> > > that
> > > it makes sense to use "=o" only and probably it is a reason why
> > > it is
> > > enough only "r". Does it make sense?
> > Probably for RISC-V can be used:
> > RISC-V—config/riscv/constraints.md
> > ...
> > A
> > An address that is held in a general-purpose register.
> > ...
>
> Just from the description I would have said no, but looking at what
> "A"
> actually expands to it is indeed RISC-V's counterpart of Arm's "Q".
> So
> yes, this looks like what amo* want to use, and then as a real
> operand,
> not just a fake one.
I am not sure that I know how to check correctly how "A" expands, but I
tried to look at code which will be generated with and without
constraints and it is the same:
// static inline void __raw_writel(uint32_t val, volatile void
__iomem *addr)
// {
// asm volatile ( "sw %0, 0(%1)" : : "r" (val), "r"(addr) );
// }
static inline void __raw_writel(uint32_t val, volatile void __iomem
*addr)
{
asm volatile ( "sw %0, %1" : : "r" (val), "Ao" (*(volatile
uint32_t __force *)addr) );
}
ffffffffc003d774: aabbd7b7 lui a5,0xaabbd
ffffffffc003d778: cdd78793 add a5,a5,-803 #
ffffffffaabbccdd <start-0x15443323>
ffffffffc003d77c: f8f42423 sw a5,-120(s0)
ffffffffc003d780: 0140000f fence w,o
>
> > AArch64 family—config/aarch64/constraints.md:
> > ...
> > Q
> > A memory address which uses a single base register with no
> > offset
> > ...
> > Also 'no offset' explains why it was added 'o' constraint for Arm
> > additionally.
>
> I don't think it does.
>
> Jan
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