[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
RE: [PATCH v12 01/37] x86/cpufeatures: Add the cpu feature bit for WRMSRNS
- To: Borislav Petkov <bp@xxxxxxxxx>
- From: "Li, Xin3" <xin3.li@xxxxxxxxx>
- Date: Tue, 14 Nov 2023 05:58:32 +0000
- Accept-language: en-US
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=P9rGz1PDhD2G2QNpTxzOiF7kPZ6vzZvmIboEtV5fAPY=; b=ml3xu00WhlKYLv4MEmPCFg+nYfGBDSilTtB9wCpCJdRhw8QKTCGyAgCJZgl41SqZq0hECqMUXVPcMyZ9zQ7GuzaRmZn6XHXbJ+IqV1/M/MJ2P1ROKN35wCz7Byekqdiy7SjwwFnIh4RgU7Hm4sGTo2/BiJc8nxKNssXN41fvd5yvDjFD4xUrd+4J/liNpGkRWK5pHKpAlCSSAph9Iyl3ihHqP+ItM+9t+wF/76V7BCsUFShaTzH7IWYRaWINwWuUINYH3xb8FWkGUwUXuMVpK3FuwS2S5YGjBYQYk1AHl9ILAeD8hZjfGm9OV82yf0CANB7ndC2AmgrOPyYTty2gTQ==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QQ9+sqvegs0a8U3tXT0H2wz72q+elbU0Fp31Lqi+s3FQUSmZwjfWGSNMq60ssmq+0MgwC0sg38gJBvQerC3N12rYtewLgcej11GDpkg8uVwxjXq1Kh/wbPzE6o5xzlklm+PxoZGK81lsv5HiwBsoUzuynImerqgZ6qvhDUqFyfqU18cuAoEAYOuWd8NWPm+/hu/FxA5gsA72t3yqFGZ0DUT82bb8Q3r4k7VD17nyI+cJ9PqpNLzQxmdreB56RSI+Dv60PiV9iYQbF2d+s22BR8/CywmHFV5rvs1SZJaPi+U/yEgWn1Boc4xeeYIZ7JNvluzc0KQJedI5WsKlrAZFQA==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com;
- Cc: "linux-doc@xxxxxxxxxxxxxxx" <linux-doc@xxxxxxxxxxxxxxx>, "linux-kernel@xxxxxxxxxxxxxxx" <linux-kernel@xxxxxxxxxxxxxxx>, "linux-edac@xxxxxxxxxxxxxxx" <linux-edac@xxxxxxxxxxxxxxx>, "linux-hyperv@xxxxxxxxxxxxxxx" <linux-hyperv@xxxxxxxxxxxxxxx>, "kvm@xxxxxxxxxxxxxxx" <kvm@xxxxxxxxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, "tglx@xxxxxxxxxxxxx" <tglx@xxxxxxxxxxxxx>, "mingo@xxxxxxxxxx" <mingo@xxxxxxxxxx>, "dave.hansen@xxxxxxxxxxxxxxx" <dave.hansen@xxxxxxxxxxxxxxx>, "x86@xxxxxxxxxx" <x86@xxxxxxxxxx>, "hpa@xxxxxxxxx" <hpa@xxxxxxxxx>, "Lutomirski, Andy" <luto@xxxxxxxxxx>, "pbonzini@xxxxxxxxxx" <pbonzini@xxxxxxxxxx>, "Christopherson,, Sean" <seanjc@xxxxxxxxxx>, "peterz@xxxxxxxxxxxxx" <peterz@xxxxxxxxxxxxx>, "Gross, Jurgen" <jgross@xxxxxxxx>, "Shankar, Ravi V" <ravi.v.shankar@xxxxxxxxx>, "mhiramat@xxxxxxxxxx" <mhiramat@xxxxxxxxxx>, "andrew.cooper3@xxxxxxxxxx" <andrew.cooper3@xxxxxxxxxx>, "jiangshanlai@xxxxxxxxx" <jiangshanlai@xxxxxxxxx>, "nik.borisov@xxxxxxxx" <nik.borisov@xxxxxxxx>
- Delivery-date: Tue, 14 Nov 2023 05:58:53 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Thread-index: AQHZ9caG3VIRGozoEkidJJiXW1l1kbBwlOyAgAieqDCAAFBGgIAADvEQ
- Thread-topic: [PATCH v12 01/37] x86/cpufeatures: Add the cpu feature bit for WRMSRNS
> and if you had to be precise, the code should do:
>
> if (cpu_feature_enabled(X86_FEATURE_FRED)) {
> if (cpu_feature_enabled(X86_FEATURE_WRMSRNS))
> wrmsrns(MSR_IA32_FRED_RSP0, (unsigned
> long)task_stack_page(task) + THREAD_SIZE);
> else
> wrmsr(MSR_IA32_FRED_RSP0, (unsigned
> long)task_stack_page(task) + THREAD_SIZE);
> }
This is exactly what tglx wanted to avoid.
And I love the idea "baseline", especially we have a ton of CPU features.
>
> > Another patch set should replace WRMSR with WRMSRNS, with SERIALIZE
> > added when needed.
>
> I sense someone wants to optimize MSR writes ... :-)
:-)
|
