[RFC PATCH 13/22] x86/vpmu: expose PDCM and IA32_PERF_CAPABILITIES when vpmu is enabled

[Edwin Török <edwin.torok@xxxxxxxxx>]

From: Edwin Török <edvin.torok@xxxxxxxxxx>

Marked as exposed by default, but then hidden if vpmu is not available.
TODO: the interaction between vpmu and policy might need some changes.

Only expose LBR and the full-width MSR capabilities, and not PEBS.

Backport: 4.15+

Signed-off-by: Edwin Török <edvin.torok@xxxxxxxxxx>
---
 xen/arch/x86/cpu-policy.c                   | 10 ++++++++--
 xen/arch/x86/hvm/vmx/vmx.c                  |  2 +-
 xen/arch/x86/msr.c                          |  8 ++++++++
 xen/arch/x86/pv/emul-priv-op.c              |  5 -----
 xen/include/public/arch-x86/cpufeatureset.h |  2 +-
 5 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index 64c8857a61..e38b648f7d 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -388,8 +388,10 @@ static void __init calculate_host_policy(void)
     recalculate_misc(p);
 
     /* When vPMU is disabled, drop it from the host policy. */
-    if ( vpmu_mode == XENPMU_MODE_OFF )
+    if ( vpmu_mode == XENPMU_MODE_OFF ) {
         p->basic.raw[0xa] = EMPTY_LEAF;
+        p->basic.pdcm = 0;
+    }
 
     if ( p->extd.svm )
     {
@@ -899,8 +901,12 @@ void recalculate_cpuid_policy(struct domain *d)
     }
 
     if ( vpmu_mode == XENPMU_MODE_OFF ||
-         ((vpmu_mode & XENPMU_MODE_ALL) && !is_hardware_domain(d)) )
+         ((vpmu_mode & XENPMU_MODE_ALL) && !is_hardware_domain(d)) ) {
         p->basic.raw[0xa] = EMPTY_LEAF;
+        p->basic.pdcm = 0;
+    }
+    if ( vpmu_features & (XENPMU_FEATURE_IPC_ONLY | XENPMU_FEATURE_ARCH_ONLY) )
+        p->basic.pdcm = 0;
 
     if ( !p->extd.svm )
         p->extd.raw[0xa] = EMPTY_LEAF;
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index f1f8a9afa2..fefd01be40 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -3602,7 +3602,7 @@ static int cf_check vmx_msr_write_intercept(
         }
 
         if (cp->basic.pmu_version >= 2 && cpu_has(&current_cpu_data, 
X86_FEATURE_PDCM)) {
-            rsvd &= ~(IA32_DEBUGCTLMSR_FREEZE_LBRS_ON_PMI | 
IA32_DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
+            rsvd &= ~(IA32_DEBUGCTLMSR_FREEZE_LBRS_ON_PMI | 
IA32_DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI | IA32_DEBUGCTLMSR_FREEZE_WHILE_SMM);
         }
 
         if ( cp->feat.rtm )
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index 0bf6d263e7..483b5e4f70 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -186,6 +186,14 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t 
*val)
             goto gp_fault;
         goto get_reg;
 
+    case MSR_IA32_PERF_CAPABILITIES:
+        if ( cp->x86_vendor != X86_VENDOR_INTEL )
+            goto gp_fault;
+        if ( !cp->basic.pdcm || rdmsr_safe(msr, *val) )
+            goto gp_fault;
+        *val &= (MSR_IA32_PERF_CAP_LBR_FORMAT | 
MSR_IA32_PERF_CAP_FREEZE_WHILE_SMM | MSR_IA32_PERF_CAP_FULLWIDTH_PMC);
+        break;
+
     case MSR_X2APIC_FIRST ... MSR_X2APIC_LAST:
         if ( !is_hvm_domain(d) || v != curr )
             goto gp_fault;
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index a8472fc779..e623e57b55 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -960,11 +960,6 @@ static int cf_check read_msr(
         *val = guest_misc_enable(*val);
         return X86EMUL_OKAY;
 
-    case MSR_IA32_PERF_CAPABILITIES:
-        /* No extra capabilities are supported. */
-        *val = 0;
-        return X86EMUL_OKAY;
-
     case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR_LAST:
     case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL_LAST:
     case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTRn:
diff --git a/xen/include/public/arch-x86/cpufeatureset.h 
b/xen/include/public/arch-x86/cpufeatureset.h
index 6b6ce2745c..0aa3251397 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -118,7 +118,7 @@ XEN_CPUFEATURE(SSSE3,         1*32+ 9) /*A  Supplemental 
Streaming SIMD Extensio
 XEN_CPUFEATURE(FMA,           1*32+12) /*A  Fused Multiply Add */
 XEN_CPUFEATURE(CX16,          1*32+13) /*A  CMPXCHG16B */
 XEN_CPUFEATURE(XTPR,          1*32+14) /*   Send Task Priority Messages */
-XEN_CPUFEATURE(PDCM,          1*32+15) /*   Perf/Debug Capability MSR */
+XEN_CPUFEATURE(PDCM,          1*32+15) /*A  Perf/Debug Capability MSR */
 XEN_CPUFEATURE(PCID,          1*32+17) /*H  Process Context ID */
 XEN_CPUFEATURE(DCA,           1*32+18) /*   Direct Cache Access */
 XEN_CPUFEATURE(SSE4_1,        1*32+19) /*A  Streaming SIMD Extensions 4.1 */
-- 
2.41.0