[PATCH v6 10/10] drivers/char: use smp barriers in xhci driver

[Marek Marczykowski-Górecki <marmarek@xxxxxxxxxxxxxxxxxxxxxx>]

All (interesting) data is in plain WB cached memory, and the few BAR
register that are configured have a UC mapping, which orders properly
WRT other writes on x86.

Suggested-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Signed-off-by: Marek Marczykowski-Górecki <marmarek@xxxxxxxxxxxxxxxxxxxxxx>
---
New in v6
---
 xen/drivers/char/xhci-dbc.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/xen/drivers/char/xhci-dbc.c b/xen/drivers/char/xhci-dbc.c
index 829f1d1d910f..03df4d82a623 100644
--- a/xen/drivers/char/xhci-dbc.c
+++ b/xen/drivers/char/xhci-dbc.c
@@ -666,7 +666,7 @@ static void dbc_pop_events(struct dbc *dbc)
 
     BUILD_BUG_ON((1 << XHCI_TRB_SHIFT) != sizeof(struct xhci_trb));
 
-    rmb();
+    smp_rmb();
 
     while ( xhci_trb_cyc(event) == er->cyc )
     {
@@ -710,7 +710,7 @@ static void dbc_pop_events(struct dbc *dbc)
     }
 
     erdp = er->dma + (er->deq << XHCI_TRB_SHIFT);
-    wmb();
+    smp_wmb();
     writeq(erdp, &reg->erdp);
 }
 
@@ -847,9 +847,9 @@ static void dbc_enable_dbc(struct dbc *dbc)
 {
     struct dbc_reg *reg = dbc->dbc_reg;
 
-    wmb();
+    smp_wmb();
     writel(readl(&reg->ctrl) | (1U << DBC_CTRL_DCE), &reg->ctrl);
-    wmb();
+    smp_wmb();
 
     while ( (readl(&reg->ctrl) & (1U << DBC_CTRL_DCE)) == 0 )
         cpu_relax();
@@ -858,9 +858,9 @@ static void dbc_enable_dbc(struct dbc *dbc)
     if ( !dbc->open )
         dbc_reset_debug_port(dbc);
 
-    wmb();
+    smp_wmb();
     writel(readl(&reg->portsc) | (1U << DBC_PSC_PED), &reg->portsc);
-    wmb();
+    smp_wmb();
 
     while ( (readl(&reg->ctrl) & (1U << DBC_CTRL_DCR)) == 0 )
         cpu_relax();
@@ -871,7 +871,7 @@ static void dbc_disable_dbc(struct dbc *dbc)
     struct dbc_reg *reg = dbc->dbc_reg;
 
     writel(readl(&reg->portsc) & ~(1U << DBC_PSC_PED), &reg->portsc);
-    wmb();
+    smp_wmb();
     writel(readl(&reg->ctrl) & ~(1U << DBC_CTRL_DCE), &reg->ctrl);
 
     while ( readl(&reg->ctrl) & (1U << DBC_CTRL_DCE) )
@@ -1032,7 +1032,7 @@ static bool dbc_ensure_running(struct dbc *dbc)
     {
         writel(ctrl | (1U << DBC_CTRL_DRC), &reg->ctrl);
         writel(readl(&reg->portsc) | (1U << DBC_PSC_PED), &reg->portsc);
-        wmb();
+        smp_wmb();
         dbc_ring_doorbell(dbc, dbc->dbc_iring.db);
         dbc_ring_doorbell(dbc, dbc->dbc_oring.db);
     }
@@ -1074,7 +1074,7 @@ static void dbc_flush(struct dbc *dbc, struct 
xhci_trb_ring *trb,
         }
     }
 
-    wmb();
+    smp_wmb();
     dbc_ring_doorbell(dbc, trb->db);
 }
 
@@ -1101,7 +1101,7 @@ static void dbc_enqueue_in(struct dbc *dbc, struct 
xhci_trb_ring *trb,
     dbc_push_trb(dbc, trb, wrk->dma + wrk->enq,
                  dbc_work_ring_space_to_end(wrk));
 
-    wmb();
+    smp_wmb();
     writel(db, &reg->db);
 }
 
-- 
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