[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: x86/PV: (lack of) MTRR exposure
On 02.05.22 16:50, Jan Beulich wrote: On 02.05.2022 16:25, Juergen Gross wrote:PAT MSR writes can be handled by special casing in xen_write_msr_safe().You can squash the write attempt there, but that'll still confuse the caller assuming the write actually took effect. With the list of cpus supported by Xen I don't see a big challenge here. PAT virtualization handles everything we need. Juergen Attachment:
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