[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 0/3] amd/msr: implement MSR_VIRT_SPEC_CTRL for HVM guests
- To: <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Roger Pau Monne <roger.pau@xxxxxxxxxx>
- Date: Tue, 15 Mar 2022 15:18:04 +0100
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Bg8XsokNI9BTbZP2j0kZdtOCd/WehMCLEDrmvQYDE00=; b=T/gpEThYBaBrsfzhOgBfvcGNm9fEI6nOVV7NkMltlpS8lbXoqUEfQqWHfBjvLmq/WU1cwh+JKD48LnU4LgXBXTL4daUiE+ucOnRnUwowIoN+NSOWWa4qSypr5ydS8wPtHAbC1NxFGd/u12r/Olo9QOJxDDLxZDDkmAqJVHpKJB9dsJX109vOIZq70IYscPkK+ZOfTKvhmu4fn9CJPLbLIj8QUMMNA3/fAbPJuz53Eb6wVvUQtO4DuwfwZEk830dD/xYooWdgrcYt5PgA/F7kRpef8o87/RQwUX+1k756ZsAecExPsUqEJJNVe62YzOyuqBSfFGjMLxMuO8vVFGNm7A==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bBJaLXkdFWrrBKdyxkk54eAeV0StClXDneqv606POtqfEuzwNnMpNnUFjSdFmdLksJNU8O9oamAScNu42Qmz2DQ4QX4ySkGzRAVOCFDNAJcXzdDwfo48aL8ZNIlNG25xRm+C4d22z4hhnlwRnx082CHw5tZ1tB27/L16gwqWfKXUyzwNAFNBaW2HR5hBYyJ6iqUH5aEv2VdiG6GzpN4boYaHD3X4rV2XxH81yop9jT62q08YmQeTKI/fk9FZfs7d3LXTvcd+aZ8lppM0EDJ5bNt/Aco4Di24pGDZ6zu3FKwv6Xf3xkDUSqnm1cCtTCj0P/lR/lvGNOobM1aN2x/5xw==
- Authentication-results: esa1.hc3370-68.iphmx.com; dkim=pass (signature verified) header.i=@citrix.onmicrosoft.com
- Cc: Roger Pau Monne <roger.pau@xxxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
- Delivery-date: Tue, 15 Mar 2022 14:18:31 +0000
- Ironport-data: A9a23:jbBnzqx8oeTE+eOSxt16t+cgxirEfRIJ4+MujC+fZmUNrF6WrkUAy 2YeWT/VPa2LZDP8ct0gaYu+8R5UsJDcx9M2HQZpqyAxQypGp/SeCIXCJC8cHc8zwu4v7q5Dx 59DAjUVBJlsFhcwnj/0bv656yMUOZigHtIQMsadUsxKbVIiGX9JZS5LwbZj2NYz2IXhWGthh PupyyHhEA79s9JLGjp8B5Kr8HuDa9yr5Vv0FnRnDRx6lAe2e0s9VfrzFonoR5fMeaFGH/bSe gr25OrRElU1XfsaIojNfr7TKiXmS1NJVOSEoiI+t6OK2nCuqsGuu0qS2TV1hUp/0l20c95NJ Nplp8WIbFYCMbT2vs8ebDYHAzNXFqlN9+qSSZS/mZT7I0zudnLtx7NlDV0sPJ1e8eFyaY1M3 aVGcnZXNEnF3r/ohuLgIgVvrp1LwM3DJoQQt2sm1TjEJf0nXYrCU+PB4towMDIY2J4QTauDP JdxhTxHZQ36eiNSNAsuEMw9uduXu3yibnpzgQfAzUYwyzeKl1EguFT3C/LKfvSaSMMTmVyXz krE9WnkBhARNPSE1CGItHmrg4fnjS79HY4fCrC83vprm0GIgHweDgUMUlm2quX/jVSxM++zM GRNpHBo9/JrshX2EJ+tBHVUvUJooDYOAuJ1QsY18Tur4anrzFmJFEEvSjVOPYlOWNANeRQm0 VqAntXMDDNpsaGIRX/1yop4vQ9eKgBOczZcOHZsoR8tpoC6/dpt1k6nosNLSvbdszHjJd3nL 9lmRgAajq5bs8ME3r7TEbvv02P1/cihouLYC2zqsoOZAuFROdbNi2+AswGzARN8wGCxFQHpU J8swZT20Qz2JcvR/BFhuc1UdF1T296LMSfHnXlkFIQ7+jKm9haLJN4Mv2svfh4zYp9eI1cFh XM/XysKvfe/21PwMcdKj3+ZUZx2ncAM6/y4PhwrUja+SscoL1LWlM2fTUWRw3rsgCARfVIXY v+mnTKXJS9CU8xPlWPuL89EiOND7n1ulAv7GMGgpzz6gOX2WZJgYepcWLd4Rrtit/3sTcS82 4s3CvZmPD0ECbygOHaLqdBPRb3IRFBiba3LRwVsXrfrCiJtGX07Cu+XxrUkeod/mL9SmPuO9 Xa4MnK0AnKl7ZEbAW1mskxeVY4=
- Ironport-hdrordr: A9a23:Luukla3JrY3SmL0pZgV71QqjBNEkLtp133Aq2lEZdPU1SKylfq WV98jzuiWYtN98YhsdcLO7WZVoP0myyXcd2+B4AV7IZmXbUQWTQr1f0Q==
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
Hello,
The following series implements support for MSR_VIRT_SPEC_CTRL
(VIRT_SSBD) on different AMD CPU families.
Note that the support is added backwards, starting with the newer CPUs
that support MSR_SPEC_CTRL and moving to the older ones either using
MSR_VIRT_SPEC_CTRL or the SSBD bit in LS_CFG.
Xen is still free to use it's own SSBD setting, as the selection is
context switched on vm{entry,exit}.
On Zen2 and later, SPEC_CTRL.SSBD exists and should be used in
preference to VIRT_SPEC_CTRL.SSBD. However, for migration
compatibility, Xen offers VIRT_SSBD to guests (in the max CPUID policy,
not default) implemented in terms of SPEC_CTRL.SSBD.
On Fam15h thru Zen1, Xen exposes VIRT_SSBD to guests by default to
abstract away the model and/or hypervisor specific differences in
MSR_LS_CFG/MSR_VIRT_SPEC_CTRL.
Note that if the hardware itself does offer VIRT_SSBD (ie: very likely
when running virtualized on < Zen2 hardware) and not AMD_SSBD Xen will
allow untrapped access to MSR_VIRT_SPEC_CTRL for HVM guests.
So the implementation of VIRT_SSBD exposed to HVM guests will use one of
the following underlying mechanisms, in the preference order listed
below:
* SPEC_CTRL.SSBD. (patch 1)
* VIRT_SPEC_CTRL.SSBD (untrapped). (patch 2).
* Non-architectural way using LS_CFG. (patch 3)
Thanks, Roger.
Roger Pau Monne (3):
amd/msr: implement VIRT_SPEC_CTRL for HVM guests on top of SPEC_CTRL
amd/msr: allow passthrough of VIRT_SPEC_CTRL for HVM guests
amd/msr: implement VIRT_SPEC_CTRL for HVM guests using legacy SSBD
xen/arch/x86/cpu/amd.c | 116 +++++++++++++++++---
xen/arch/x86/cpuid.c | 28 +++++
xen/arch/x86/hvm/hvm.c | 1 +
xen/arch/x86/hvm/svm/entry.S | 6 +
xen/arch/x86/hvm/svm/svm.c | 49 +++++++++
xen/arch/x86/include/asm/amd.h | 4 +
xen/arch/x86/include/asm/cpufeatures.h | 1 +
xen/arch/x86/include/asm/msr.h | 14 +++
xen/arch/x86/msr.c | 27 +++++
xen/arch/x86/spec_ctrl.c | 12 +-
xen/include/public/arch-x86/cpufeatureset.h | 2 +-
11 files changed, 241 insertions(+), 19 deletions(-)
--
2.34.1
|
