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[PATCH 3/3] x86/Intel: use CPUID bit to determine PPIN availability
- To: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Thu, 27 Jan 2022 16:09:40 +0000
- Authentication-results: esa6.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none
- Cc: Jan Beulich <jbeulich@xxxxxxxx>, Jan Beulich <JBeulich@xxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
- Delivery-date: Thu, 27 Jan 2022 16:10:06 +0000
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- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
From: Jan Beulich <jbeulich@xxxxxxxx>
As of SDM revision 076 there is a CPUID bit for this functionality. Use
it to amend the existing model-based logic.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
CC: Jan Beulich <JBeulich@xxxxxxxx>
CC: Roger Pau Monné <roger.pau@xxxxxxxxxx>
CC: Wei Liu <wl@xxxxxxx>
Split in two.
---
tools/misc/xen-cpuid.c | 1 +
xen/arch/x86/cpu/mcheck/mce_intel.c | 10 +++++++++-
xen/include/public/arch-x86/cpufeatureset.h | 1 +
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index 17e67e379fa4..3c8f3ed1bad1 100644
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -197,6 +197,7 @@ static const char *const str_e21a[32] =
static const char *const str_7b1[32] =
{
+ [ 0] = "ppin",
};
static const struct {
diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c
b/xen/arch/x86/cpu/mcheck/mce_intel.c
index d0161e9d4daa..d63d6083d3a7 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -859,12 +859,20 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
/*
* Even if testing the presence of the MSR would be enough, we don't
* want to risk the situation where other models reuse this MSR for
- * other purposes.
+ * other purposes. Despite the late addition of a CPUID bit (rendering
+ * the MSR architectural), keep using the same detection logic there.
*/
switch ( c->x86_model )
{
uint64_t val;
+ default:
+ if ( !cpu_has(c, X86_FEATURE_INTEL_PPIN) )
+ {
+ ppin_msr = 0;
+ return;
+ }
+ fallthrough;
case 0x3e: /* IvyBridge X */
case 0x3f: /* Haswell X */
case 0x4f: /* Broadwell X */
diff --git a/xen/include/public/arch-x86/cpufeatureset.h
b/xen/include/public/arch-x86/cpufeatureset.h
index 588f924de59e..6e44148a0901 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -300,6 +300,7 @@ XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE
always serializing */
XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Base
(and limit too) */
/* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */
+XEN_CPUFEATURE(INTEL_PPIN, 12*32+ 0) /* Protected Processor
Inventory Number */
#endif /* XEN_CPUFEATURE */
--
2.11.0
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