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Re: [PATCH] x86/Intel: use CPUID bit to determine PPIN availability
- To: Andrew Cooper <amc96@xxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Wed, 19 Jan 2022 08:15:04 +0100
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Wed, 19 Jan 2022 07:15:23 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 18.01.2022 21:28, Andrew Cooper wrote:
> On 17/01/2022 15:30, Jan Beulich wrote:
>> As of SDM revision 076 there is a CPUID bit for this functionality. Use
>> it to amend the existing model-based logic.
>>
>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
>
> https://lore.kernel.org/lkml/20220107225442.1690165-1-tony.luck@xxxxxxxxx/T/#u
> suggests that Sapphire Rapids also needs the model specific treatment.
Well, I can go and pull in their a331f5fdd36 just to be on the safe side.
I have to admit that it's not clear to me whether that older commit is
made obsolete by the CPUID bit check about to be added.
> I agree with the "only-expose-on-error" observation, so perhaps we ought
> to make these details available to the hardware domain in a suitable form.
hypfs?
Jan
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