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Re: [PATCH v3 5/6] x86/vpic: issue dpci EOI for cleared pins at ICW1

On 27.01.2021 10:15, Roger Pau Monné wrote:
> On Tue, Jan 26, 2021 at 05:57:49PM +0100, Jan Beulich wrote:
>> On 26.01.2021 14:45, Roger Pau Monne wrote:
>>> When pins are cleared from either ISR or IRR as part of the
>>> initialization sequence forward the clearing of those pins to the dpci
>>> EOI handler, as it is equivalent to an EOI. Not doing so can bring the
>>> interrupt controller state out of sync with the dpci handling logic,
>>> that expects a notification when a pin has been EOI'ed.
>>> Fixes: 7b3cb5e5416 ('IRQ injection changes for HVM PCI passthru.')
>>> Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
>> As said before, under the assumption that the clearing of IRR
>> and ISR that we do is correct, I agree with the change. I'd
>> like to give it some time though before giving my R-b here, for
>> the inquiry to hopefully get answered. After all there's still
>> the possibility of us needing to instead squash that clearing
>> (which then would seem to result in getting things in sync the
>> other way around).
> OK, let's wait a bit to see what Intel replies. I assume this would
> qualify as a bugfix for getting it committed later?

It would be up to Ian then to judge, but as long as it fixes an
actual bug, my understanding is it will still qualify for being




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