[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v3 4/6] x86/vpic: don't trigger unmask event until end of init
- To: <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Roger Pau Monne <roger.pau@xxxxxxxxxx>
- Date: Tue, 26 Jan 2021 14:45:19 +0100
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=lofouQ1GmU+o4c970v6OlV6XbO/TLQaARJUEc3j0n3k=; b=BXzpCHLEJryuCFja8jv62rgGIgvYTo/ISDWyZpdmsZwyWJf3qbGCVdy0XerWaFXCHGqHI5OcBWf0lIIJYp+iWsWGFly/4zdjM5/8ePjezF2jFmGS8JgMP2JDs1JNPFbkOsElvAjY8sNKT2Gr1Fq8EJqDU1K9b0wECuVO+0fQII7WoHkK+OznVHFrNQrs20F44wIbD1VzGsfv5bNlMTxn8zPUq76DRfgMNxwWlhO+IQlv6gjralITqG5uJUc/HC1xpbeJihoWd7rhqnVsi+rzJTosi+lyQfTFKgsxDv5VyiaqOZkqg3RZFG8mINkl3Lu8KvrCei+1klkwRHM/TFmYfA==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iMoJcsqoW1/mvojvG54F9OjG1uuBdJ0mOwE1XTWMv42/mkmLaShXAfSbjKkAjX/5X2s3BrgFhNqdqGzzY01QfuLNY0bydFZ2uFfGOwWIjju8q9x5g5Fu6o2SOCvVoSJoxDJJ8Kuvo1bXhBCdAQk76r0CNlPvxzFspWI98byWaHPr4SgX9bUkPoP5C1p/c2djCgt02mURvYIu0tq79z470c+jg1hD4pjfzwC0LNZW6etbWQw5YXNwLK9rQgnOO8BZz/Kf2jKMmyEa3qTSunOZVwZmJhy488WpqAiLadRbThNAqsZPP+H4MMfP+FdHYcvJB+jX8BJNXwFyD6qJ3sj82w==
- Authentication-results: esa3.hc3370-68.iphmx.com; dkim=pass (signature verified) header.i=@citrix.onmicrosoft.com
- Cc: Roger Pau Monne <roger.pau@xxxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
- Delivery-date: Tue, 26 Jan 2021 13:46:44 +0000
- Ironport-sdr: AUV6PQw5FuQcSYh6wUuQzGLp4pqaQH++62YaT8Bn1pn+ffeLhOw8TzuNUNGjfInMV6denFAcde trDGoJaGvquRfSC9Dp8jvynriDn+v35NGn1hYbxWrIZjO8nvf92Q0KCDiCMeW9XSQ36/v5Jjzg S9nCouRKueMl4ucx5ErvWVEPnKlqUeDaEZItLkd6CU3YcGYPbkBuUakqTcS73/gUZyP2XLP5M6 wMiRbEy8WO/njovXDJB3kdrm5tZoiqzCsaYZ+qbGkoWawAwr6kwyz4JSoDiUyzm6h/l7IQyaBz Qxw=
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
Wait until the end of the init sequence to trigger the unmask event.
Note that it will be unconditionally triggered, but that's harmless if
not unmask actually happened.
While there change the variable type to bool.
Requested-by: Jan Beulich <jbeulich@xxxxxxxx>
Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
---
Changes since v2:
- New in this version.
---
xen/arch/x86/hvm/vpic.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/hvm/vpic.c b/xen/arch/x86/hvm/vpic.c
index 9195155ff0..795a76768d 100644
--- a/xen/arch/x86/hvm/vpic.c
+++ b/xen/arch/x86/hvm/vpic.c
@@ -188,7 +188,8 @@ static void vpic_ioport_write(
struct hvm_hw_vpic *vpic, uint32_t addr, uint32_t val)
{
int priority, cmd;
- uint8_t mask, unmasked = 0;
+ uint8_t mask;
+ bool unmasked = false;
vpic_lock(vpic);
@@ -200,7 +201,6 @@ static void vpic_ioport_write(
/* Clear edge-sensing logic. */
vpic->irr &= vpic->elcr;
- unmasked = vpic->imr;
/* No interrupts masked or in service. */
vpic->imr = vpic->isr = 0;
@@ -294,13 +294,17 @@ static void vpic_ioport_write(
/* ICW3 */
vpic->init_state++;
if ( !(vpic->init_state & 4) )
+ {
vpic->init_state = 0; /* No ICW4: init done */
+ unmasked = true;
+ }
break;
case 3:
/* ICW4 */
vpic->special_fully_nested_mode = (val >> 4) & 1;
vpic->auto_eoi = (val >> 1) & 1;
vpic->init_state = 0;
+ unmasked = true;
break;
}
}
--
2.29.2
|