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[PATCH v2 2/4] x86/vioapic: issue EOI to dpci when switching pin to edge trigger mode
- To: <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Roger Pau Monne <roger.pau@xxxxxxxxxx>
- Date: Fri, 15 Jan 2021 15:28:18 +0100
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- Cc: Roger Pau Monne <roger.pau@xxxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
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When an IO-APIC pin is switched from level to edge trigger mode the
IRR bit is cleared, so it can be used as a way to EOI an interrupt at
the IO-APIC level.
Such EOI however does not get forwarded to the dpci code like it's
done for the local APIC initiated EOI. This change adds the code in
order to notify dpci of such EOI, so that dpci and the interrupt
controller are in sync.
Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
---
xen/arch/x86/hvm/vioapic.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c
index 804bc77279..dc35347afa 100644
--- a/xen/arch/x86/hvm/vioapic.c
+++ b/xen/arch/x86/hvm/vioapic.c
@@ -268,6 +268,17 @@ static void vioapic_write_redirent(
spin_unlock(&d->arch.hvm.irq_lock);
+ if ( ent.fields.trig_mode == VIOAPIC_EDGE_TRIG &&
+ ent.fields.remote_irr && is_iommu_enabled(d) )
+ /*
+ * Since IRR has been cleared and further interrupts can be
+ * injected also attempt to deassert any virtual line of passed
+ * through devices using this pin. Switching a pin from level to
+ * trigger mode can be used as a way to EOI an interrupt at the
+ * IO-APIC level.
+ */
+ hvm_dpci_eoi(d, gsi);
+
if ( is_hardware_domain(d) && unmasked )
{
/*
--
2.29.2
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