[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH 5/5] x86/PV32: avoid TLB flushing after mod_l3_entry()
On 11.01.2021 15:23, Roger Pau Monné wrote: > On Tue, Nov 03, 2020 at 11:58:16AM +0100, Jan Beulich wrote: >> 32-bit guests may not depend upon the side effect of using ordinary >> 4-level paging when running on a 64-bit hypervisor. For L3 entry updates >> to take effect, they have to use a CR3 reload. Therefore there's no need >> to issue a paging structure invalidating TLB flush in this case. > > I assume it's fine for the Xen linear page tables to be lkely out of > sync during the windows between the entry update and the CR3 reload? Yes, because ... > I wonder, won't something similar also apply to 64bit and L4 entries? ... unlike 64-bit paging, PAE paging special cases the treatment of the 4 top level table entries. On bare metal they get loaded by the CPU upon CR3 load, not when walking page tables. Jan
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