[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH 5/5] x86/PV32: avoid TLB flushing after mod_l3_entry()


  • To: Jan Beulich <jbeulich@xxxxxxxx>
  • From: Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • Date: Mon, 11 Jan 2021 15:23:08 +0100
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FHRk73s3AgDtrZPMOOqUQvKTNlhuIzJKKvGbnKCIMF8=; b=dgq24890LYa8IkJl6tX8WeBws64cRWS58/fOVi8NVXNlECJsu5aWzI6lCBkiy6mhrVyCfe0xNsjJEWCMQwsFk5s0i3uCrOZkuKNOW2EUjGa72YOJOltqAXoz1MT9GW2Uljw+nbBhHQdvDDJdkN2uLZjs/oF4hMX7WKb1Yu6YH33IB2JzoTIlbsRYBcrBupDgPFuc1wsK+QqVmGghPPSrEO5+xksRLO+t5elG401d5LYHn6A/XqvzTzOLs1wgz439e8c6heoCWYNdRG0YmbEXwEL6wGwa1yWDVRsgtJ5XjXsb4qsSP7pJqRiV0xJPohPUYIKYmqa4F2oBdD90YTDzGg==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Fz8q0my3C+yWFXv2Uo1EsBelE8fNR7HtafHz/cH+p6jYvlKDSX0RZNuEk29Ym4JRK6qh9pM5oIv5ozd694oM77s8oeHSWoMfh4LDmrm3BfPGJNm+phmKruStY/g41YLlTz/9yRrI6HwKjPwxOThBTcP8FCFFMY0j8XGIWTGsyuyBEg7Iw1Y0cos27tM0EOFRx0QymfwgwjGCtOfaArV4GK6IVVw80GDx/7q8w+Fzqj6YMrx4CNfKK/1gDCLnonBwnHiyuZb3lf4FSL+faEJCrLC9wXSy7bS/QfjxnCxDoDkA0/WEaxrJtwONwRkdunqKBk35gL9CI3+ovJ/B5HgdQw==
  • Authentication-results: esa2.hc3370-68.iphmx.com; dkim=pass (signature verified) header.i=@citrix.onmicrosoft.com
  • Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, George Dunlap <george.dunlap@xxxxxxxxxx>
  • Delivery-date: Mon, 11 Jan 2021 14:23:25 +0000
  • Ironport-sdr: uXqGgVn3oq01JTA9sRSt5Xf1n1olUdrLTaIYNL8tgxnOuEMPjHa2LbcHAY80nnYUoCRaA9TyC6 QuPw4vQ0MsVXP4aoZQEfpIRwPnH442cjxS+SITdFiuDDU/LO4TzEX7o+BUUUguHr2wH3mYZAsm cVC25v6BBFEjfOhViOaG5/Hkm/RWrZdX4lCk2kLLlBZYJUTYOARfP9cpCcfp4DfJbubJjXs570 OV4pdBT2aeqo7W/2GyG4YPo22M6q0fryoM/A1wxNf7+Pv0K5kOr7OSgQtWmoUNICWmCAT26LN0 Mp0=
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On Tue, Nov 03, 2020 at 11:58:16AM +0100, Jan Beulich wrote:
> 32-bit guests may not depend upon the side effect of using ordinary
> 4-level paging when running on a 64-bit hypervisor. For L3 entry updates
> to take effect, they have to use a CR3 reload. Therefore there's no need
> to issue a paging structure invalidating TLB flush in this case.

I assume it's fine for the Xen linear page tables to be lkely out of
sync during the windows between the entry update and the CR3 reload?

I wonder, won't something similar also apply to 64bit and L4 entries?

Thanks, Roger.



 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.