[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH for-4.14] x86/msr: Disallow access to Processor Trace MSRs
We do not expose the feature to guests, so should disallow access to the respective MSRs. Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> --- CC: Jan Beulich <JBeulich@xxxxxxxx> CC: Wei Liu <wl@xxxxxxx> CC: Roger Pau Monné <roger.pau@xxxxxxxxxx> CC: Paul Durrant <paul@xxxxxxx> CC: Michał Leszczyński <michal.leszczynski@xxxxxxx> Paul: For 4.14. This needs backporting to older trees as well. Michał: CC'ing, just to keep you in the loop. Xen has some dubious default MSR semantics which we're still in the middle of untangling in a backwards compatible way. Patches like this will eventually not be necessary, but they are for now. --- xen/arch/x86/msr.c | 12 ++++++++++++ xen/include/asm-x86/msr-index.h | 8 ++++++++ 2 files changed, 20 insertions(+) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 0bfb5839b2..05afe601a8 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -168,6 +168,12 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) case MSR_TSX_FORCE_ABORT: case MSR_TSX_CTRL: case MSR_MCU_OPT_CTRL: + case MSR_RTIT_OUTPUT_BASE: + case MSR_RTIT_OUTPUT_MASK: + case MSR_RTIT_CTL: + case MSR_RTIT_STATUS: + case MSR_RTIT_CR3_MATCH: + case MSR_RTIT_ADDR_A(0) ... MSR_RTIT_ADDR_B(3): case MSR_U_CET: case MSR_S_CET: case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE: @@ -329,6 +335,12 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) case MSR_TSX_FORCE_ABORT: case MSR_TSX_CTRL: case MSR_MCU_OPT_CTRL: + case MSR_RTIT_OUTPUT_BASE: + case MSR_RTIT_OUTPUT_MASK: + case MSR_RTIT_CTL: + case MSR_RTIT_STATUS: + case MSR_RTIT_CR3_MATCH: + case MSR_RTIT_ADDR_A(0) ... MSR_RTIT_ADDR_B(3): case MSR_U_CET: case MSR_S_CET: case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE: diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index b328a47ed8..0fe98af923 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -69,6 +69,14 @@ #define MSR_MCU_OPT_CTRL 0x00000123 #define MCU_OPT_CTRL_RNGDS_MITG_DIS (_AC(1, ULL) << 0) +#define MSR_RTIT_OUTPUT_BASE 0x00000560 +#define MSR_RTIT_OUTPUT_MASK 0x00000561 +#define MSR_RTIT_CTL 0x00000570 +#define MSR_RTIT_STATUS 0x00000571 +#define MSR_RTIT_CR3_MATCH 0x00000572 +#define MSR_RTIT_ADDR_A(n) (0x00000580 + (n) * 2) +#define MSR_RTIT_ADDR_B(n) (0x00000581 + (n) * 2) + #define MSR_U_CET 0x000006a0 #define MSR_S_CET 0x000006a2 #define CET_SHSTK_EN (_AC(1, ULL) << 0) -- 2.11.0
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