Re: [Xen-devel] [PATCH v2 04/10] x86: Add Intel Processor Trace MSRs and bit definitions

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 03.07.18 at 12:18, <luwei.kang@xxxxxxxxx> wrote:
>> > --- a/xen/include/asm-x86/msr-index.h
>> > +++ b/xen/include/asm-x86/msr-index.h
>> > @@ -548,4 +548,41 @@
>> >  #define MSR_PKGC9_IRTL                    0x00000634
>> >  #define MSR_PKGC10_IRTL                   0x00000635
>> >
>> > +/* Intel PT MSRs */
>> > +#define MSR_IA32_RTIT_CTL         0x00000570
>> > +#define RTIT_CTL_TRACEEN          (1ULL << 0)
>> > +#define RTIT_CTL_CYCEN                    (1ULL << 1)
>> > +#define RTIT_CTL_OS                       (1ULL << 2)
>> > +#define RTIT_CTL_USR                      (1ULL << 3)
>> > +#define RTIT_CTL_PWR_EVT_EN               (1ULL << 4)
>> > +#define RTIT_CTL_FUP_ON_PTW               (1ULL << 5)
>> > +#define RTIT_CTL_FABRIC_EN                (1ULL << 6)
>> > +#define RTIT_CTL_CR3_FILTER               (1ULL << 7)
>> > +#define RTIT_CTL_TOPA                     (1ULL << 8)
>> > +#define RTIT_CTL_MTC_EN                   (1ULL << 9)
>> > +#define RTIT_CTL_TSC_EN                   (1ULL << 10)
>> > +#define RTIT_CTL_DIS_RETC         (1ULL << 11)
>> > +#define RTIT_CTL_PTW_EN                   (1ULL << 12)
>> > +#define RTIT_CTL_BRANCH_EN                (1ULL << 13)
>> > +#define RTIT_CTL_MTC_FREQ_OFFSET  14
>> > +#define RTIT_CTL_MTC_FREQ         (0x0fULL << RTIT_CTL_MTC_FREQ_OFFSET)
>> 
>> No duplicates like these please - with MASK_EXTR() / MASK_INSR() having just 
> the mask (and no offset/shift value) is sufficient.
> 
> OK, get it. I just need to define
> +#define RTIT_CTL_MTC_FREQ            (0x0fULL << RTIT_CTL_MTC_FREQ_OFFSET)

#define RTIT_CTL_MTC_FREQ               (0x0fULL << 14)

you mean, I assume?

Jan



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