Re: [Xen-devel] [PATCH 00/25 v7] SBSA UART emulation support in Xen

[Julien Grall <julien.grall@xxxxxxx>]

Hi,

A quick update below.

On 14/08/17 14:54, Julien Grall wrote:
> On 14/08/17 08:52, Bhupinder Thakur wrote:
> > I could not reproduce the issue with the reduced buffer of 16 bytes
> > also. I think it may not be reproducible on the foundation model. I am
> > trying to bring up xen on an ARM machine here to reproduce the issue.
> >
> > While looking at the pl011 driver in linux, I see one potential case
> > where the the driver may send more data even when the TX FIFO is full.
> > It seems the pl011 driver expects that the TX interrupt must be raised
> > only when at least half of TX FIFO queue is empty.
> >
> > pl011_tx_chars() calls pl011_tx_char() in a loop for (fifosize/2)
> > number of times. Since these APIs are getting called in the interrupt
> > context, pl011_tx_char() does not check for TX FIFO full status
> > because it expects that fifosize/2 space is available.
> >
> > In the emulation logic, we should set the TX bit in the status
> > register only if at least space for 16 bytes is available (since SBSA
> > fifosize is 32). Currently, we may be setting the TX bit even if there
> > is space for 1 byte. In that scenario, the driver may write more data
> > then emulation logic can queue up.
> I understand that it is the behavior expected by Linux. However did you
> check it was compliant with the spec?
>
> If I looked at the PL011 (ARM DDI 0183G), the interrupt FIFO level is
> set via UARTIFLS. The reset value is half-way mark (i.e 16 byte).
>
> However, looking at the SBSA, this register is inexistent and I can't
> find anything mentioning the half-way mark. So we need some
> clarification here. Let me ask it.
>
> Meanwhile, trying the half-way mark would be good to see if it helps.
I got the confirmation that some clarification is needed in the spec. 
Until this is done, we should assume the halfway mark in our emulation.
Cheers,

> Cheers,
--
Julien Grall

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