Re: [Xen-devel] [RFC v2]Proposal to allow setting up shared memory areas between VMs from xl config file

[Julien Grall <julien.grall@xxxxxxx>]

Hi Stefano,

On 06/23/2017 07:21 PM, Stefano Stabellini wrote:
> On Fri, 23 Jun 2017, Julien Grall wrote:
> > Hi,
> >
> > On 22/06/17 22:05, Stefano Stabellini wrote:
> > > > When we encounter an id IDx during "xl create":
> > > >
> > > >    + If it’s not under /local/shared_mem:
> > > >      + If the corresponding entry has a "master" tag, create the
> > > >        corresponding entries for IDx in xenstore
> > > >      + If there isn't a "master" tag, say error.
> > > >
> > > >    + If it’s found under /local/shared_mem:
> > > >      + If the corresponding entry has a "master" tag, say error
> > > >      + If there isn't a "master" tag, map the pages to the newly
> > > >        created domain, and add the current domain and necessary information
> > > >        under /local/shared_mem/IDx/slaves.
> > > Aside from using "gfn" instead of gmfn everywhere, I think it looks
> > > pretty good.
> > >
> > > I would leave out permissions and cacheability attributes from this
> > > version of the work. I would just add a note saying that memory will be
> > > mapped as RW regular cacheable RAM. Other permissions and cacheability
> > > will be possible, but they are not implemented yet.
> > Well, I think we should design the interface correctly from the beginning to
> > facilitate future extension.
> Which interface are you speaking about?
The interface with the user, i.e libxl and xl. The hypercall can be 
added later if necessary as this could be a DOMCTL so not part of a 
stable ABI.
> I don't think we should attemp to write how the hypercall interface
> might look like in the future to support setting permissions and
> cacheability attributes.
>
>
> > Also, you need to clarify what you mean by "regular cacheable RAM". Are they
> > write-through, write-back...? But, on ARM, this would only be the caching
> > attribute in stage-2 page table. The final caching, memory type, shareability
> > would be a combination of stage-2 and stage-1 attributes.
> The very same that is used today for the ram of virtual machines, do we
> need to say any more than that? (For ARM, p2m_ram_rw and MATTR_MEM,
> LPAE_SH_INNER. For stage1, we should refer to
> xen/include/public/arch-arm.h.)
 * All memory which is shared with other entities in the system
 * (including the hypervisor and other guests) must reside in memory
 * which is mapped as Normal Inner-cacheable. This applies to:
 *  - hypercall arguments passed via a pointer to guest memory.
 *  - memory shared via the grant table mechanism (including PV I/O
 *    rings etc).
 *  - memory shared with the hypervisor (struct shared_info, struct
 *
 * Any Inner cache allocation strategy (Write-Back, Write-Through etc)
 * is acceptable. There is no restriction on the Outer-cacheability.

This does not include memory shared between guest via other method than 
grant-table. So the documentation should be at least updated.
But AFAICT, this does not say anything about the shareability of the 
region. It only speaks about outer-cache and inner-cache.
Cheers,

--
Julien Grall

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