Re: [Xen-devel] [PATCH v2 17/30] x86/cpu: Common infrastructure for levelling context switching

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 16.02.16 at 15:15, <JBeulich@xxxxxxxx> wrote:
>>>> On 05.02.16 at 14:42, <andrew.cooper3@xxxxxxxxxx> wrote:
>> --- a/xen/include/asm-x86/processor.h
>> +++ b/xen/include/asm-x86/processor.h
>> @@ -574,6 +574,34 @@ void microcode_set_module(unsigned int);
>>  int microcode_update(XEN_GUEST_HANDLE_PARAM(const_void), unsigned long len);
>>  int microcode_resume_cpu(unsigned int cpu);
>>  
>> +#define LCAP_faulting (1U << 0)
>> +#define LCAP_1cd      (3U << 1)
>> +#define LCAP_e1cd     (3U << 3)
>> +#define LCAP_Da1      (1U << 5)
>> +#define LCAP_6c       (1U << 6)
>> +#define LCAP_7ab0     (3U << 7)
> 
> I guess the cases where the mask has two set bits is when two
> CPUID output registers are being controlled, but I don't see
> what use that pairing is going to be. But with the patch
> supposedly going to make sense only in the context of the
> following ones, I'll see (and I'd presumably be able to ack this
> one then also only when having seen the others).

Having seen patches up to and including 21, I still don't see the
point of using 2-bit masks here.

Jan


_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxx
http://lists.xen.org/xen-devel