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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH RFC XEN v1 02/14] xen: arm: Provide a mechanism to read (and decode) an LR from a saved VCPU
On Wed, 9 Dec 2015, Ian Campbell wrote:
> This will allow generic vgic save code to get at this state without needing
> to know about gic v2 vs v3 etc.
>
> Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
Acked-by: Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
> xen/arch/arm/gic-v2.c | 20 ++++++++++++++++----
> xen/arch/arm/gic-v3.c | 21 ++++++++++++++++-----
> xen/arch/arm/gic.c | 5 +++++
> xen/include/asm-arm/gic.h | 7 +++++++
> 4 files changed, 44 insertions(+), 9 deletions(-)
>
> diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
> index 01e36b5..5cc4cc3 100644
> --- a/xen/arch/arm/gic-v2.c
> +++ b/xen/arch/arm/gic-v2.c
> @@ -417,11 +417,8 @@ static void gicv2_clear_lr(int lr)
> writel_gich(0, GICH_LR + lr * 4);
> }
>
> -static void gicv2_read_lr(int lr, struct gic_lr *lr_reg)
> +static void gicv2_decode_lr_value(uint32_t lrv, struct gic_lr *lr_reg)
> {
> - uint32_t lrv;
> -
> - lrv = readl_gich(GICH_LR + lr * 4);
> lr_reg->pirq = (lrv >> GICH_V2_LR_PHYSICAL_SHIFT) &
> GICH_V2_LR_PHYSICAL_MASK;
> lr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) &
> GICH_V2_LR_VIRTUAL_MASK;
> lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) &
> GICH_V2_LR_PRIORITY_MASK;
> @@ -430,6 +427,14 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg)
> lr_reg->grp = (lrv >> GICH_V2_LR_GRP_SHIFT) & GICH_V2_LR_GRP_MASK;
> }
>
> +static void gicv2_read_lr(int lr, struct gic_lr *lr_reg)
> +{
> + uint32_t lrv;
> +
> + lrv = readl_gich(GICH_LR + lr * 4);
> + gicv2_decode_lr_value(lrv, lr_reg);
> +}
> +
> static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg)
> {
> uint32_t lrv = 0;
> @@ -447,6 +452,12 @@ static void gicv2_write_lr(int lr, const struct gic_lr
> *lr_reg)
> writel_gich(lrv, GICH_LR + lr * 4);
> }
>
> +static void gicv2_vcpu_saved_lr(const struct vcpu *v, int lr,
> + struct gic_lr *lr_val)
> +{
> + gicv2_decode_lr_value(v->arch.gic.v2.lr[lr], lr_val);
> +}
> +
> static void gicv2_hcr_status(uint32_t flag, bool_t status)
> {
> uint32_t hcr = readl_gich(GICH_HCR);
> @@ -746,6 +757,7 @@ const static struct gic_hw_operations gicv2_ops = {
> .save_state = gicv2_save_state,
> .restore_state = gicv2_restore_state,
> .dump_state = gicv2_dump_state,
> + .vcpu_saved_lr = gicv2_vcpu_saved_lr,
> .gic_host_irq_type = &gicv2_host_irq_type,
> .gic_guest_irq_type = &gicv2_guest_irq_type,
> .eoi_irq = gicv2_eoi_irq,
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index 4fe0c37..342aa4a 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -908,12 +908,8 @@ static void gicv3_clear_lr(int lr)
> gicv3_ich_write_lr(lr, 0);
> }
>
> -static void gicv3_read_lr(int lr, struct gic_lr *lr_reg)
> +static void gicv3_decode_lr_value(uint64_t lrv, struct gic_lr *lr_reg)
> {
> - uint64_t lrv;
> -
> - lrv = gicv3_ich_read_lr(lr);
> -
> lr_reg->pirq = (lrv >> GICH_LR_PHYSICAL_SHIFT) & GICH_LR_PHYSICAL_MASK;
> lr_reg->virq = (lrv >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK;
>
> @@ -923,6 +919,14 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg)
> lr_reg->grp = (lrv >> GICH_LR_GRP_SHIFT) & GICH_LR_GRP_MASK;
> }
>
> +static void gicv3_read_lr(int lr, struct gic_lr *lr_reg)
> +{
> + uint64_t lrv;
> +
> + lrv = gicv3_ich_read_lr(lr);
> + gicv3_decode_lr_value(lrv, lr_reg);
> +}
> +
> static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr)
> {
> uint64_t lrv = 0;
> @@ -937,6 +941,12 @@ static void gicv3_write_lr(int lr_reg, const struct
> gic_lr *lr)
> gicv3_ich_write_lr(lr_reg, lrv);
> }
>
> +static void gicv3_vcpu_saved_lr(const struct vcpu *v, int lr,
> + struct gic_lr *lr_val)
> +{
> + gicv3_decode_lr_value(v->arch.gic.v3.lr[lr], lr_val);
> +}
> +
> static void gicv3_hcr_status(uint32_t flag, bool_t status)
> {
> uint32_t hcr;
> @@ -1298,6 +1308,7 @@ static const struct gic_hw_operations gicv3_ops = {
> .save_state = gicv3_save_state,
> .restore_state = gicv3_restore_state,
> .dump_state = gicv3_dump_state,
> + .vcpu_saved_lr = gicv3_vcpu_saved_lr,
> .gic_host_irq_type = &gicv3_host_irq_type,
> .gic_guest_irq_type = &gicv3_guest_irq_type,
> .eoi_irq = gicv3_eoi_irq,
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index bea39d6..8d219e3 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -108,6 +108,11 @@ void gic_restore_state(struct vcpu *v)
> gic_restore_pending_irqs(v);
> }
>
> +void gic_vcpu_saved_lr(const struct vcpu *v, int lr, struct gic_lr *lr_val)
> +{
> + gic_hw_ops->vcpu_saved_lr(v, lr, lr_val);
> +}
> +
> /*
> * needs to be called with a valid cpu_mask, ie each cpu in the mask has
> * already called gic_cpu_init
> diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
> index 818384b..b6516f4 100644
> --- a/xen/include/asm-arm/gic.h
> +++ b/xen/include/asm-arm/gic.h
> @@ -263,6 +263,10 @@ extern int gicv_setup(struct domain *d);
> extern void gic_save_state(struct vcpu *v);
> extern void gic_restore_state(struct vcpu *v);
>
> +/* Save/restore */
> +extern void gic_vcpu_saved_lr(const struct vcpu *v, int lr,
> + struct gic_lr *lr_val);
> +
> /* SGI (AKA IPIs) */
> enum gic_sgi {
> GIC_SGI_EVENT_CHECK = 0,
> @@ -318,6 +322,9 @@ struct gic_hw_operations {
> /* Dump GIC LR register information */
> void (*dump_state)(const struct vcpu *);
>
> + /* Get saved LR state */
> + void (*vcpu_saved_lr)(const struct vcpu *v, int lr, struct gic_lr
> *lr_val);
> +
> /* hw_irq_controller to enable/disable/eoi host irq */
> hw_irq_controller *gic_host_irq_type;
>
> --
> 2.6.1
>
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