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Re: [Xen-devel] [PATCH v10 6/7] vmx: VT-d posted-interrupt core logic handling



> From: Wu, Feng
> Sent: Friday, December 11, 2015 9:59 AM
>
> > > +void vmx_vcpu_block(struct vcpu *v)
> > > +{
> > > +    unsigned long flags;
> > > +    struct pi_desc *pi_desc = &v->arch.hvm_vmx.pi_desc;
> > > +
> > > +    if ( !has_arch_pdevs(v->domain) )
> > > +        return;
> > > +
> > > +    ASSERT(v->arch.hvm_vmx.pi_block_cpu == NR_CPUS);
> > > +
> > > +    /*
> > > +     * The vCPU is blocking, we need to add it to one of the per pCPU 
> > > lists.
> > > +     * We save v->processor to v->arch.hvm_vmx.pi_block_cpu and use it 
> > > for
> > > +     * the per-CPU list, we also save it to posted-interrupt descriptor 
> > > and
> > > +     * make it as the destination of the wake-up notification event.
> >
> > the 2nd piece - "we also save it to posted-interrupt descriptor" is not
> > reflected within this function. Do you mean "we have saved it to..."
> > or "we will save it later to..." in other places?

what about this question?

> >
> > > +
> > > +    ack_APIC_irq();
> > > +    this_cpu(irq_count)++;
> > > +
> > > +    spin_lock(lock);
> > > +
> > > +    /*
> > > +     * XXX: The length of the list depends on how many vCPU is current
> > > +     * blocked on this specific pCPU. This may hurt the interrupt latency
> > > +     * if the list grows to too many entries.
> > > +     */
> > > +    list_for_each_entry_safe(vmx, tmp, blocked_vcpus, 
> > > pi_blocked_vcpu_list)
> > > +    {
> > > +        if ( pi_test_on(&vmx->pi_desc) )
> > > +        {
> > > +            list_del(&vmx->pi_blocked_vcpu_list);
> > > +            vmx->pi_block_cpu = NR_CPUS;
> > > +            v = container_of(vmx, struct vcpu, arch.hvm_vmx);
> > > +            vcpu_unblock(v);
> > > +        }
> > > +    }
> > > +
> > > +    spin_unlock(lock);
> > > +}
> > > +
> >
> > I may miss something here. Who will clear ON bit? test read?
> 
> There are two places where ON can get clear.
> - In vmx_sync_pir_to_irr() during sync interrupts information from
> PIR to IRR
> - If the guest is running in non-root, the CPU hardware will clear
> 'ON' when handling the notification event. No vm-exits in this case.
> 

Thanks for explanation. It makes sense to me. Indeed no need to
clear ON here.

Thanks
Kevin

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