Re: [Xen-devel] [PATCH] iommu/quirk: disable shared EPT for Sandybridge and earlier processors.

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

On 03/12/15 08:50, Tian, Kevin wrote:
>> From: Jan Beulich [mailto:JBeulich@xxxxxxxx]
>> Sent: Thursday, December 03, 2015 4:18 PM
>>
>>>>> On 03.12.15 at 03:40, <kevin.tian@xxxxxxxxx> wrote:
>>> Just confirmed internally with HW team. On SNB 4KB cache is always
>>> used regardless of 4KB/2MB/1GB mapping. There'd be another reason
>>> for this 40% drop observation...
>> So when they stated that the 4k TLB gets always used, did they at
>> least provide some thoughts on what else might be causing this
>> severe a performance impact? Without them helping we're left
>> guessing...
>>
> Unfortunately no clear answer...

http://networkbuilders.intel.com/docs/Network_Builders_RA_vBRAS_Final.pdf

Page 42: "The IOTLB on the previous generation Intel Xeon Processor
E5-2690 does not natively support huge pages (it emulates them using 4K
pages)."

And Figure 51 on Page 43

The "emulates them using 4K pages" probably means that the IOTLB is
flushed and filled with 512 adjacent 4k mappings.

Citrix's measurements back up the findings in that paper, and also show
that performance is better when using plain 4k mappings as opposed to
emulated 2M mappings.

~Andrew

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