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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v5.99.1 RFC 2/4] xen/arm: Make gic-v2 code handle hip04-d01 platform
The GIC in this platform is mainly compatible with the standard
GICv2 beside:
- ITARGET is extended to 16 bit to support 16 CPUs;
- SGI mask is extended to support 16 CPUs;
- maximum supported interrupt is 510.
Use nr_lines to check for maximum irq supported. hip04-d01 support less
interrupts due to some field restriction. Any value above this is already
an error.
Signed-off-by: Frediano Ziglio <frediano.ziglio@xxxxxxxxxx>
Signed-off-by: Zoltan Kiss <zoltan.kiss@xxxxxxxxxx>
---
xen/arch/arm/domain_build.c | 1 +
xen/arch/arm/gic-hip04.c | 43 +++++++++++++++++++++++++------------------
xen/arch/arm/gic.c | 3 ++-
xen/include/asm-arm/gic.h | 3 +++
4 files changed, 31 insertions(+), 19 deletions(-)
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index c2dcb49..0834053 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -1038,6 +1038,7 @@ static int handle_node(struct domain *d, struct
kernel_info *kinfo,
static const struct dt_device_match gic_matches[] __initconst =
{
DT_MATCH_GIC_V2,
+ DT_MATCH_GIC_HIP04,
DT_MATCH_GIC_V3,
{ /* sentinel */ },
};
diff --git a/xen/arch/arm/gic-hip04.c b/xen/arch/arm/gic-hip04.c
index a401e3f..9a7ed46 100644
--- a/xen/arch/arm/gic-hip04.c
+++ b/xen/arch/arm/gic-hip04.c
@@ -1,7 +1,8 @@
/*
- * xen/arch/arm/gic-v2.c
+ * xen/arch/arm/gic-hip04.c
*
- * ARM Generic Interrupt Controller support v2
+ * ARM Generic Interrupt Controller support for HiSilicon Hip04 platform
+ * Based heavily from gic-v2.c
*
* Tim Deegan <tim@xxxxxxx>
* Copyright (c) 2011 Citrix Systems.
@@ -79,16 +80,24 @@ static struct gic_info gicv2_info;
* logical CPU numbering. Let's use mapping as returned by the GIC
* itself
*/
-static DEFINE_PER_CPU(u8, gic_cpu_id);
+static DEFINE_PER_CPU(u16, gic_cpu_id);
/* Maximum cpu interface per GIC */
-#define NR_GIC_CPU_IF 8
+#define NR_GIC_CPU_IF 16
+
+#undef GICD_SGI_TARGET_SHIFT
+#define GICD_SGI_TARGET_SHIFT 8
static inline void writeb_gicd(uint8_t val, unsigned int offset)
{
writeb_relaxed(val, gicv2.map_dbase + offset);
}
+static inline void writew_gicd(uint16_t val, unsigned int offset)
+{
+ writew_relaxed(val, gicv2.map_dbase + offset);
+}
+
static inline void writel_gicd(uint32_t val, unsigned int offset)
{
writel_relaxed(val, gicv2.map_dbase + offset);
@@ -230,7 +239,7 @@ static void gicv2_set_irq_properties(struct irq_desc *desc,
writel_gicd(cfg, GICD_ICFGR + (irq / 16) * 4);
/* Set target CPU mask (RAZ/WI on uniprocessor) */
- writeb_gicd(mask, GICD_ITARGETSR + irq);
+ writew_gicd(mask, GICD_ITARGETSR + irq * 2);
/* Set priority */
writeb_gicd(priority, GICD_IPRIORITYR + irq);
@@ -244,8 +253,7 @@ static void __init gicv2_dist_init(void)
uint32_t gic_cpus;
int i;
- cpumask = readl_gicd(GICD_ITARGETSR) & 0xff;
- cpumask |= cpumask << 8;
+ cpumask = readl_gicd(GICD_ITARGETSR) & 0xffff;
cpumask |= cpumask << 16;
/* Disable the distributor */
@@ -253,7 +261,7 @@ static void __init gicv2_dist_init(void)
type = readl_gicd(GICD_TYPER);
gicv2_info.nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1);
- gic_cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5);
+ gic_cpus = 16;
printk("GICv2: %d lines, %d cpu%s%s (IID %8.8x).\n",
gicv2_info.nr_lines, gic_cpus, (gic_cpus == 1) ? "" : "s",
(type & GICD_TYPE_SEC) ? ", secure" : "",
@@ -264,8 +272,8 @@ static void __init gicv2_dist_init(void)
writel_gicd(0x0, GICD_ICFGR + (i / 16) * 4);
/* Route all global IRQs to this CPU */
- for ( i = 32; i < gicv2_info.nr_lines; i += 4 )
- writel_gicd(cpumask, GICD_ITARGETSR + (i / 4) * 4);
+ for ( i = 32; i < gicv2_info.nr_lines; i += 2 )
+ writel_gicd(cpumask, GICD_ITARGETSR + (i / 2) * 4);
/* Default priority for global interrupts */
for ( i = 32; i < gicv2_info.nr_lines; i += 4 )
@@ -285,7 +293,7 @@ static void __cpuinit gicv2_cpu_init(void)
{
int i;
- this_cpu(gic_cpu_id) = readl_gicd(GICD_ITARGETSR) & 0xff;
+ this_cpu(gic_cpu_id) = readl_gicd(GICD_ITARGETSR) & 0xffff;
/* The first 32 interrupts (PPI and SGI) are banked per-cpu, so
* even though they are controlled with GICD registers, they must
@@ -579,7 +587,7 @@ static void gicv2_irq_set_affinity(struct irq_desc *desc,
const cpumask_t *cpu_m
mask = gicv2_cpu_mask(cpu_mask);
/* Set target CPU mask (RAZ/WI on uniprocessor) */
- writeb_gicd(mask, GICD_ITARGETSR + desc->irq);
+ writew_gicd(mask, GICD_ITARGETSR + desc->irq * 2);
spin_unlock(&gicv2.lock);
}
@@ -765,19 +773,18 @@ static int __init gicv2_init(struct dt_device_node *node,
const void *data)
return 0;
}
-static const char * const gicv2_dt_compat[] __initconst =
+static const char * const hip04_gicv2_dt_compat[] __initconst =
{
- DT_COMPAT_GIC_CORTEX_A15,
- DT_COMPAT_GIC_CORTEX_A7,
- DT_COMPAT_GIC_400,
+ DT_COMPAT_GIC_HIP04,
NULL
};
-DT_DEVICE_START(gicv2, "GICv2:", DEVICE_GIC)
- .compatible = gicv2_dt_compat,
+DT_DEVICE_START(hip04_gicv2, "GICv2:", DEVICE_GIC)
+ .compatible = hip04_gicv2_dt_compat,
.init = gicv2_init,
DT_DEVICE_END
+
/*
* Local variables:
* mode: C
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 390c8b0..e4512a8 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -565,12 +565,13 @@ static void do_sgi(struct cpu_user_regs *regs, enum
gic_sgi sgi)
void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
{
unsigned int irq;
+ unsigned int max_irq = gic_hw_ops->info->nr_lines;
do {
/* Reading IRQ will ACK it */
irq = gic_hw_ops->read_irq();
- if ( likely(irq >= 16 && irq < 1021) )
+ if ( likely(irq >= 16 && irq < max_irq) )
{
local_irq_enable();
do_IRQ(regs, irq, is_fiq);
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 187dc46..f245c50 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -155,11 +155,14 @@
#define DT_COMPAT_GIC_400 "arm,gic-400"
#define DT_COMPAT_GIC_CORTEX_A15 "arm,cortex-a15-gic"
#define DT_COMPAT_GIC_CORTEX_A7 "arm,cortex-a7-gic"
+#define DT_COMPAT_GIC_HIP04 "hisilicon,hip04-intc"
#define DT_MATCH_GIC_V2 DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A15), \
DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A7), \
DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_400)
+#define DT_MATCH_GIC_HIP04 DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_HIP04)
+
#define DT_COMPAT_GIC_V3 "arm,gic-v3"
#define DT_MATCH_GIC_V3 DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_V3)
--
1.9.1
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